TimeQuest Timing Analyzer report for Epson
Mon Oct 15 23:33:16 2012
Quartus II 32-bit Version 12.0 Build 178 05/31/2012 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 13. Slow 1200mV 85C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 14. Slow 1200mV 85C Model Setup: 'CLK_BRD'
 15. Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'
 16. Slow 1200mV 85C Model Setup: 'SW_USER4'
 17. Slow 1200mV 85C Model Setup: 'SW_USER3'
 18. Slow 1200mV 85C Model Setup: 'SW_USER2'
 19. Slow 1200mV 85C Model Hold: 'SW_USER3'
 20. Slow 1200mV 85C Model Hold: 'SW_USER4'
 21. Slow 1200mV 85C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 22. Slow 1200mV 85C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 23. Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'
 24. Slow 1200mV 85C Model Hold: 'SW_USER2'
 25. Slow 1200mV 85C Model Hold: 'CLK_BRD'
 26. Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'
 27. Slow 1200mV 85C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 28. Slow 1200mV 85C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 29. Slow 1200mV 85C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 30. Slow 1200mV 85C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 31. Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER3'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER2'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER4'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 39. Setup Times
 40. Hold Times
 41. Clock to Output Times
 42. Minimum Clock to Output Times
 43. Propagation Delay
 44. Minimum Propagation Delay
 45. Slow 1200mV 85C Model Metastability Report
 46. Slow 1200mV 0C Model Fmax Summary
 47. Slow 1200mV 0C Model Setup Summary
 48. Slow 1200mV 0C Model Hold Summary
 49. Slow 1200mV 0C Model Recovery Summary
 50. Slow 1200mV 0C Model Removal Summary
 51. Slow 1200mV 0C Model Minimum Pulse Width Summary
 52. Slow 1200mV 0C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 53. Slow 1200mV 0C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 54. Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 55. Slow 1200mV 0C Model Setup: 'CLK_BRD'
 56. Slow 1200mV 0C Model Setup: 'SW_USER4'
 57. Slow 1200mV 0C Model Setup: 'SW_USER2'
 58. Slow 1200mV 0C Model Setup: 'SW_USER3'
 59. Slow 1200mV 0C Model Hold: 'SW_USER3'
 60. Slow 1200mV 0C Model Hold: 'SW_USER4'
 61. Slow 1200mV 0C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 62. Slow 1200mV 0C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 63. Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
 64. Slow 1200mV 0C Model Hold: 'SW_USER2'
 65. Slow 1200mV 0C Model Hold: 'CLK_BRD'
 66. Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
 67. Slow 1200mV 0C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 68. Slow 1200mV 0C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 69. Slow 1200mV 0C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 70. Slow 1200mV 0C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 71. Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
 72. Slow 1200mV 0C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER3'
 76. Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER2'
 77. Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER4'
 78. Slow 1200mV 0C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 79. Setup Times
 80. Hold Times
 81. Clock to Output Times
 82. Minimum Clock to Output Times
 83. Propagation Delay
 84. Minimum Propagation Delay
 85. Slow 1200mV 0C Model Metastability Report
 86. Fast 1200mV 0C Model Setup Summary
 87. Fast 1200mV 0C Model Hold Summary
 88. Fast 1200mV 0C Model Recovery Summary
 89. Fast 1200mV 0C Model Removal Summary
 90. Fast 1200mV 0C Model Minimum Pulse Width Summary
 91. Fast 1200mV 0C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 92. Fast 1200mV 0C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
 93. Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 94. Fast 1200mV 0C Model Setup: 'CLK_BRD'
 95. Fast 1200mV 0C Model Setup: 'SW_USER3'
 96. Fast 1200mV 0C Model Setup: 'SW_USER4'
 97. Fast 1200mV 0C Model Setup: 'SW_USER2'
 98. Fast 1200mV 0C Model Hold: 'SW_USER3'
 99. Fast 1200mV 0C Model Hold: 'SW_USER4'
100. Fast 1200mV 0C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
101. Fast 1200mV 0C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
102. Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
103. Fast 1200mV 0C Model Hold: 'SW_USER2'
104. Fast 1200mV 0C Model Hold: 'CLK_BRD'
105. Fast 1200mV 0C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
106. Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
107. Fast 1200mV 0C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
108. Fast 1200mV 0C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
109. Fast 1200mV 0C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
110. Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
111. Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
112. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
113. Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER3'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER4'
115. Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER2'
116. Fast 1200mV 0C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
117. Fast 1200mV 0C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'
118. Setup Times
119. Hold Times
120. Clock to Output Times
121. Minimum Clock to Output Times
122. Propagation Delay
123. Minimum Propagation Delay
124. Fast 1200mV 0C Model Metastability Report
125. Multicorner Timing Analysis Summary
126. Setup Times
127. Hold Times
128. Clock to Output Times
129. Minimum Clock to Output Times
130. Progagation Delay
131. Minimum Progagation Delay
132. Board Trace Model Assignments
133. Input Transition Times
134. Slow Corner Signal Integrity Metrics
135. Fast Corner Signal Integrity Metrics
136. Setup Transfers
137. Hold Transfers
138. Recovery Transfers
139. Removal Transfers
140. Report TCCS
141. Report RSKM
142. Unconstrained Paths
143. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 12.0 Build 178 05/31/2012 SJ Web Edition ;
; Revision Name      ; Epson                                            ;
; Device Family      ; Cyclone III                                      ;
; Device Name        ; EP3C40F780C8                                     ;
; Timing Models      ; Final                                            ;
; Delay Model        ; Combined                                         ;
; Rise/Fall Delays   ; Enabled                                          ;
+--------------------+--------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; Epson_sta.sdc ; OK     ; Mon Oct 15 23:33:00 2012 ;
+---------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------------------------------------------------------------------------+
; Clock Name                                                                       ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                                                              ;
+----------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------------------------------------------------------------------------+
; CLK_BRD                                                                          ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK_BRD }                                                                          ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] } ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] }    ;
; JTAG_NEXUS_TCK                                                                   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { JTAG_NEXUS_TCK }                                                                   ;
; SW_USER2                                                                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { SW_USER2 }                                                                         ;
; SW_USER3                                                                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { SW_USER3 }                                                                         ;
; SW_USER4                                                                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { SW_USER4 }                                                                         ;
+----------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                              ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                       ; Note                                                          ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
; 88.46 MHz  ; 88.46 MHz       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;                                                               ;
; 163.69 MHz ; 163.69 MHz      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;                                                               ;
; 185.25 MHz ; 185.25 MHz      ; CLK_BRD                                                                          ;                                                               ;
; 186.05 MHz ; 186.05 MHz      ; JTAG_NEXUS_TCK                                                                   ;                                                               ;
; 341.18 MHz ; 250.0 MHz       ; SW_USER4                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
; 343.17 MHz ; 250.0 MHz       ; SW_USER3                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
; 346.26 MHz ; 250.0 MHz       ; SW_USER2                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                       ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -9.795 ; -601.528      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -5.109 ; -38.100       ;
; CLK_BRD                                                                          ; -4.398 ; -110.574      ;
; JTAG_NEXUS_TCK                                                                   ; -4.375 ; -866.070      ;
; SW_USER4                                                                         ; -1.931 ; -12.925       ;
; SW_USER3                                                                         ; -1.914 ; -13.758       ;
; SW_USER2                                                                         ; -1.888 ; -12.184       ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                        ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; SW_USER3                                                                         ; -1.777 ; -1.777        ;
; SW_USER4                                                                         ; -1.390 ; -10.721       ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.588 ; -1.361        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.504 ; -3.024        ;
; JTAG_NEXUS_TCK                                                                   ; 0.451  ; 0.000         ;
; SW_USER2                                                                         ; 0.497  ; 0.000         ;
; CLK_BRD                                                                          ; 0.758  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                    ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; JTAG_NEXUS_TCK                                                                   ; -2.696 ; -60.785       ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -2.514 ; -15.058       ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -1.723 ; -30.316       ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                     ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.208 ; -0.208        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.570  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                   ; 1.847  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                         ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -3.201 ; -245.105      ;
; JTAG_NEXUS_TCK                                                                   ; -3.000 ; -374.750      ;
; CLK_BRD                                                                          ; -3.000 ; -49.097       ;
; SW_USER3                                                                         ; -3.000 ; -17.101       ;
; SW_USER2                                                                         ; -3.000 ; -14.896       ;
; SW_USER4                                                                         ; -3.000 ; -14.896       ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.487 ; -23.792       ;
+----------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                            ; To Node                                                                   ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -9.795 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.705     ;
; -9.795 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.705     ;
; -9.663 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.573     ;
; -9.663 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.573     ;
; -9.635 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.545     ;
; -9.635 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.545     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.370     ;
; -9.348 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.267     ;
; -9.348 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.267     ;
; -9.348 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.267     ;
; -9.348 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.267     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.328 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.238     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.300 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 10.210     ;
; -9.216 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.135     ;
; -9.216 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.135     ;
; -9.216 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.135     ;
; -9.216 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.135     ;
; -9.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.107     ;
; -9.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.107     ;
; -9.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.107     ;
; -9.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 10.107     ;
; -9.028 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.938      ;
; -9.028 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.938      ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.841 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 10.137     ;
; -8.829 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.616     ;
; -8.829 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.616     ;
; -8.824 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.610     ;
; -8.824 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.610     ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.756 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.665      ;
; -8.746 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.532     ;
; -8.746 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.532     ;
; -8.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 9.993      ;
; -8.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.305      ; 9.993      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.693 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.091     ; 9.603      ;
; -8.669 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.456     ;
; -8.669 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.456     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 10.417     ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.615 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.092     ; 9.524      ;
; -8.581 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 9.500      ;
; -8.581 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 9.500      ;
; -8.581 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 9.500      ;
; -8.581 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 9.500      ;
; -8.570 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.357     ;
; -8.570 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.796      ; 10.357     ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -5.109 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 3.110      ;
; -5.023 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 3.024      ;
; -5.007 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 3.008      ;
; -4.961 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 2.962      ;
; -4.864 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 2.865      ;
; -4.814 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 2.815      ;
; -4.758 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -3.000     ; 2.759      ;
; -3.736 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 3.277      ;
; -3.647 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 3.188      ;
; -3.637 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 3.178      ;
; -3.589 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 3.130      ;
; -3.499 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 3.040      ;
; -3.444 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 2.985      ;
; -3.349 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.460     ; 2.890      ;
; -2.826 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.190      ; 4.507      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.592 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 7.083      ;
; -2.327 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.190      ; 4.508      ;
; -2.061 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.049     ; 3.013      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.992 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 6.983      ;
; -1.940 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.049     ; 2.892      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.832 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.751      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.830 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.749      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.692 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.611      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.678 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.597      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.653 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.572      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.534 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.453      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.532 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.451      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.522 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.441      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.502 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.421      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.296      ;
; -1.370 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.289      ;
; -1.370 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.082     ; 2.289      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_BRD'                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -4.398 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.316      ;
; -4.368 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.286      ;
; -4.293 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.211      ;
; -4.263 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.181      ;
; -4.252 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.170      ;
; -4.222 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.140      ;
; -4.216 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 5.135      ;
; -4.210 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.128      ;
; -4.200 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.118      ;
; -4.191 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 5.110      ;
; -4.180 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.098      ;
; -4.177 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 5.096      ;
; -4.176 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.094      ;
; -4.162 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.080      ;
; -4.147 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.065      ;
; -4.144 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.062      ;
; -4.137 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.055      ;
; -4.117 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.035      ;
; -4.114 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.032      ;
; -4.106 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 5.024      ;
; -4.076 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.994      ;
; -4.070 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.989      ;
; -4.064 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.982      ;
; -4.054 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.972      ;
; -4.045 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.964      ;
; -4.040 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.959      ;
; -4.034 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.952      ;
; -4.031 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.950      ;
; -4.030 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.948      ;
; -4.027 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.945      ;
; -4.016 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.934      ;
; -4.015 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.934      ;
; -4.005 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.923      ;
; -4.001 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.919      ;
; -4.001 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.920      ;
; -3.998 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.916      ;
; -3.997 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.915      ;
; -3.991 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.909      ;
; -3.975 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.893      ;
; -3.971 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.889      ;
; -3.968 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.886      ;
; -3.960 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.878      ;
; -3.930 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.848      ;
; -3.924 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.843      ;
; -3.918 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.836      ;
; -3.908 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.826      ;
; -3.908 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.826      ;
; -3.899 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.818      ;
; -3.894 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.813      ;
; -3.888 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.806      ;
; -3.885 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.804      ;
; -3.884 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.802      ;
; -3.881 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.799      ;
; -3.878 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.796      ;
; -3.875 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.793      ;
; -3.872 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.791      ;
; -3.870 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.788      ;
; -3.869 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.788      ;
; -3.859 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.777      ;
; -3.855 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.773      ;
; -3.855 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.774      ;
; -3.852 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.770      ;
; -3.851 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.769      ;
; -3.845 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.763      ;
; -3.845 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.763      ;
; -3.840 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.759      ;
; -3.832 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.750      ;
; -3.829 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.747      ;
; -3.825 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.743      ;
; -3.822 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.740      ;
; -3.814 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.732      ;
; -3.813 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.732      ;
; -3.810 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.728      ;
; -3.802 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.720      ;
; -3.784 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.702      ;
; -3.780 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.698      ;
; -3.778 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.697      ;
; -3.772 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.690      ;
; -3.762 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.680      ;
; -3.762 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.680      ;
; -3.753 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.672      ;
; -3.748 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.667      ;
; -3.742 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.660      ;
; -3.739 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.658      ;
; -3.738 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.656      ;
; -3.735 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.653      ;
; -3.732 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.650      ;
; -3.729 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.647      ;
; -3.726 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.645      ;
; -3.724 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.642      ;
; -3.723 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.642      ;
; -3.713 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.631      ;
; -3.709 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.627      ;
; -3.709 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.628      ;
; -3.706 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.624      ;
; -3.705 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.623      ;
; -3.699 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.617      ;
; -3.699 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.083     ; 4.617      ;
; -3.696 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.615      ;
; -3.694 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.082     ; 4.613      ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                                                                                                ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -4.375 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.261      ;
; -4.375 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.261      ;
; -4.375 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.261      ;
; -4.296 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.202      ;
; -4.296 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.202      ;
; -4.296 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.202      ;
; -4.296 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.202      ;
; -4.290 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.196      ;
; -4.290 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.196      ;
; -4.290 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.196      ;
; -4.290 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.196      ;
; -4.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.153      ;
; -4.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.153      ;
; -4.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.153      ;
; -4.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 5.136      ;
; -4.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.114      ;
; -4.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.114      ;
; -4.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.114      ;
; -4.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.114      ;
; -4.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.114      ;
; -4.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 5.130      ;
; -4.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.107     ; 5.100      ;
; -4.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.107     ; 5.100      ;
; -4.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.107     ; 5.100      ;
; -4.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.107     ; 5.100      ;
; -4.189 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.107      ;
; -4.189 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.107      ;
; -4.189 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.107      ;
; -4.184 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.070      ;
; -4.184 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.070      ;
; -4.184 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 5.070      ;
; -4.183 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.101      ;
; -4.183 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.101      ;
; -4.183 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.101      ;
; -4.170 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.088      ;
; -4.170 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.088      ;
; -4.170 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 5.088      ;
; -4.152 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.058      ;
; -4.152 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.058      ;
; -4.152 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.058      ;
; -4.152 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 5.058      ;
; -4.139 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 5.034      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_0__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.111 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.997      ;
; -4.085 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 4.992      ;
; -4.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.966      ;
; -4.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.966      ;
; -4.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.966      ;
; -4.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.966      ;
; -4.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.966      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 4.964      ;
; -4.065 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.951      ;
; -4.065 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.951      ;
; -4.065 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.951      ;
; -4.060 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.946      ;
; -4.060 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.946      ;
; -4.060 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.946      ;
; -4.055 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.941      ;
; -4.055 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.941      ;
; -4.055 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_5__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.941      ;
; -4.055 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.941      ;
; -4.045 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.963      ;
; -4.045 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.963      ;
; -4.045 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.963      ;
; -4.006 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.912      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.116     ; 4.888      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.116     ; 4.888      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.116     ; 4.888      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.116     ; 4.888      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_0__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.889      ;
; -4.000 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.906      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_10__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
; -3.999 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.115     ; 4.885      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SW_USER4'                                                                                                                                                                                                                                                                                         ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.931 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.851      ;
; -1.917 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.837      ;
; -1.890 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.810      ;
; -1.857 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.777      ;
; -1.832 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.751      ;
; -1.829 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.748      ;
; -1.772 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.691      ;
; -1.744 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.664      ;
; -1.735 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.654      ;
; -1.732 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.651      ;
; -1.686 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.605      ;
; -1.675 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.594      ;
; -1.651 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.570      ;
; -1.626 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.545      ;
; -1.621 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.540      ;
; -1.600 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.520      ;
; -1.576 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.495      ;
; -1.561 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.480      ;
; -1.529 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.448      ;
; -1.505 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.424      ;
; -1.479 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.398      ;
; -1.430 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.349      ;
; -1.430 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.349      ;
; -1.391 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.310      ;
; -1.383 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.302      ;
; -1.361 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.280      ;
; -1.357 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.276      ;
; -1.342 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.081     ; 2.262      ;
; -1.328 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.247      ;
; -1.328 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.247      ;
; -1.325 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.244      ;
; -1.325 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.244      ;
; -1.286 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.205      ;
; -1.285 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.204      ;
; -1.283 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.202      ;
; -1.282 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.201      ;
; -1.281 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.200      ;
; -1.194 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.113      ;
; -1.159 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.078      ;
; -1.150 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.069      ;
; -1.150 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.069      ;
; -1.108 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.027      ;
; -1.107 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.026      ;
; -1.107 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.026      ;
; -1.106 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.025      ;
; -1.106 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.025      ;
; -1.088 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 2.007      ;
; -1.017 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.936      ;
; -1.017 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.936      ;
; -0.975 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.894      ;
; -0.974 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.893      ;
; -0.973 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.892      ;
; -0.973 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.892      ;
; -0.815 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.734      ;
; -0.783 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.702      ;
; -0.644 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.563      ;
; -0.481 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.082     ; 1.400      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.462  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.577      ; 4.606      ;
; 0.522  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.576      ; 4.545      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.232  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.448      ; 6.697      ;
; 1.292  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 7.447      ; 6.636      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.422  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.448      ; 7.007      ;
; 1.482  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 7.447      ; 6.946      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SW_USER3'                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.914 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.833      ;
; -1.846 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.765      ;
; -1.782 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.701      ;
; -1.771 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.690      ;
; -1.697 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.616      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.692 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.610      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.677 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.595      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.665 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.583      ;
; -1.624 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.543      ;
; -1.618 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.537      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.565 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.483      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.496 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.414      ;
; -1.493 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.411      ;
; -1.463 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.381      ;
; -1.416 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.334      ;
; -1.416 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.334      ;
; -1.416 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.334      ;
; -1.416 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.334      ;
; -1.416 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.334      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.302      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.381 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.083     ; 2.299      ;
; -1.152 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 2.071      ;
; 0.061  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.082     ; 0.858      ;
; 1.319  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.971      ;
; 1.460  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.830      ;
; 1.466  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.824      ;
; 1.466  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.824      ;
; 1.503  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.787      ;
; 1.588  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.702      ;
; 1.590  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.700      ;
; 1.661  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.799      ; 3.629      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SW_USER2'                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.888 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.853      ;
; -1.876 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.841      ;
; -1.839 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.804      ;
; -1.748 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.713      ;
; -1.742 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.707      ;
; -1.713 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.678      ;
; -1.709 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.674      ;
; -1.704 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.669      ;
; -1.702 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.667      ;
; -1.697 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.662      ;
; -1.697 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.662      ;
; -1.617 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.582      ;
; -1.613 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.578      ;
; -1.597 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.562      ;
; -1.571 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.536      ;
; -1.567 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.532      ;
; -1.547 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.512      ;
; -1.512 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.477      ;
; -1.472 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.437      ;
; -1.468 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.433      ;
; -1.457 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.422      ;
; -1.451 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.416      ;
; -1.450 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.415      ;
; -1.420 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.385      ;
; -1.416 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.381      ;
; -1.389 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.354      ;
; -1.389 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.354      ;
; -1.388 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.353      ;
; -1.384 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.349      ;
; -1.382 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.347      ;
; -1.377 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.342      ;
; -1.377 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.342      ;
; -1.370 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.335      ;
; -1.368 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.333      ;
; -1.320 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.285      ;
; -1.311 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.276      ;
; -1.304 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.269      ;
; -1.271 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.236      ;
; -1.269 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.234      ;
; -1.264 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.229      ;
; -1.180 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.145      ;
; -1.166 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.131      ;
; -1.166 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.131      ;
; -1.164 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.129      ;
; -1.097 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.062      ;
; -1.096 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.061      ;
; -1.095 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.060      ;
; -1.087 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.052      ;
; -1.040 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.005      ;
; -1.038 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 2.003      ;
; -1.026 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.991      ;
; -0.984 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.949      ;
; -0.983 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.948      ;
; -0.982 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.947      ;
; -0.851 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.816      ;
; -0.851 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.056     ; 1.816      ;
; 0.114  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.049     ; 0.858      ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SW_USER3'                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.777 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.137      ;
; -1.765 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.149      ;
; -1.754 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.160      ;
; -1.745 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.169      ;
; -1.704 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.210      ;
; -1.661 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.253      ;
; -1.638 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.276      ;
; -1.624 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 5.172      ; 3.290      ;
; 0.464  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 0.758      ;
; 0.760  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.055      ;
; 0.769  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.064      ;
; 0.769  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.064      ;
; 0.770  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.065      ;
; 0.771  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.066      ;
; 0.772  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.067      ;
; 0.790  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.085      ;
; 1.015  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.309      ;
; 1.114  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.409      ;
; 1.123  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.418      ;
; 1.124  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.419      ;
; 1.130  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.425      ;
; 1.133  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.428      ;
; 1.133  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.428      ;
; 1.139  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.434      ;
; 1.142  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.437      ;
; 1.142  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.437      ;
; 1.254  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.549      ;
; 1.255  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.550      ;
; 1.263  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.558      ;
; 1.264  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.559      ;
; 1.273  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.568      ;
; 1.273  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.568      ;
; 1.282  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.577      ;
; 1.282  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.577      ;
; 1.348  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.642      ;
; 1.391  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.685      ;
; 1.395  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.690      ;
; 1.404  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.699      ;
; 1.413  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.708      ;
; 1.422  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.717      ;
; 1.488  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.782      ;
; 1.531  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.825      ;
; 1.588  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 1.883      ;
; 1.628  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.922      ;
; 1.671  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 1.965      ;
; 1.772  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.067      ;
; 1.858  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.153      ;
; 1.870  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.165      ;
; 1.876  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.171      ;
; 1.876  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.171      ;
; 1.877  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.172      ;
; 1.877  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.172      ;
; 1.877  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.172      ;
; 1.877  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.172      ;
; 1.939  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.082      ; 2.233      ;
; 1.978  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.273      ;
; 1.978  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.273      ;
; 1.978  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.273      ;
; 1.999  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.294      ;
; 2.012  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.307      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.117  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.412      ;
; 2.149  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.444      ;
; 2.184  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.479      ;
; 2.184  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.479      ;
; 2.184  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.479      ;
; 2.184  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.479      ;
; 2.184  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.083      ; 2.479      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SW_USER4'                                                                                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.390 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.743      ; 6.605      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.333 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.744      ; 6.663      ;
; -1.120 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.743      ; 6.375      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -1.063 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.744      ; 6.433      ;
; -0.478 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.010      ; 4.274      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; -0.421 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 5.011      ; 4.332      ;
; 0.972  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.266      ;
; 0.974  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.268      ;
; 1.151  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.445      ;
; 1.170  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.464      ;
; 1.170  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.464      ;
; 1.171  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.465      ;
; 1.174  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.468      ;
; 1.231  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.525      ;
; 1.235  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.529      ;
; 1.236  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.530      ;
; 1.237  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.531      ;
; 1.278  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.572      ;
; 1.280  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.574      ;
; 1.300  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.594      ;
; 1.302  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.596      ;
; 1.329  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.623      ;
; 1.339  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.634      ;
; 1.341  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.636      ;
; 1.407  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.701      ;
; 1.407  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.701      ;
; 1.409  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.703      ;
; 1.412  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.706      ;
; 1.488  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.782      ;
; 1.489  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.783      ;
; 1.513  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.807      ;
; 1.515  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.809      ;
; 1.537  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.831      ;
; 1.538  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.832      ;
; 1.541  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.835      ;
; 1.541  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.835      ;
; 1.542  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.836      ;
; 1.543  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.837      ;
; 1.550  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.844      ;
; 1.551  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.845      ;
; 1.552  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.846      ;
; 1.555  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.849      ;
; 1.559  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.853      ;
; 1.559  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.853      ;
; 1.563  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.857      ;
; 1.565  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.859      ;
; 1.598  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.893      ;
; 1.599  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.894      ;
; 1.599  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.894      ;
; 1.600  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.895      ;
; 1.603  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.083      ; 1.898      ;
; 1.631  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.925      ;
; 1.632  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.926      ;
; 1.636  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.930      ;
; 1.664  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.958      ;
; 1.681  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 1.975      ;
; 1.710  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.004      ;
; 1.712  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.006      ;
; 1.715  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.009      ;
; 1.791  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.085      ;
; 1.792  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.086      ;
; 1.793  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.087      ;
; 1.794  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.082      ; 2.088      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                             ; To Node                                                                                                          ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -0.588 ; JTAG_NEXUS_TCK                                                                                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck1_Z                                                                          ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.201      ; 3.855      ;
; -0.340 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.001      ; 2.893      ;
; -0.175 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.191      ; 4.509      ;
; -0.153 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.191      ; 4.511      ;
; -0.105 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.203      ; 4.571      ;
; 0.141  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.203      ; 4.337      ;
; 0.165  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.191      ; 4.349      ;
; 0.211  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.191      ; 4.395      ;
; 0.213  ; JTAG_NEXUS_TCK                                                                                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck1_Z                                                                          ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.201      ; 4.156      ;
; 0.284  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.203      ; 4.960      ;
; 0.284  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.203      ; 4.960      ;
; 0.292  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.633      ;
; 0.293  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.634      ;
; 0.366  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.096      ; 1.704      ;
; 0.435  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 1.762      ;
; 0.463  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.758      ;
; 0.463  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.758      ;
; 0.471  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.812      ;
; 0.491  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.832      ;
; 0.491  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.832      ;
; 0.495  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.836      ;
; 0.496  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.837      ;
; 0.500  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.795      ;
; 0.511  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.086      ; 1.839      ;
; 0.529  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.870      ;
; 0.529  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.870      ;
; 0.546  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_8__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.887      ;
; 0.555  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.896      ;
; 0.558  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.899      ;
; 0.582  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.923      ;
; 0.591  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.932      ;
; 0.602  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.943      ;
; 0.615  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.956      ;
; 0.619  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.960      ;
; 0.626  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_0__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 1.965      ;
; 0.634  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.098      ; 1.974      ;
; 0.638  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.979      ;
; 0.641  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.982      ;
; 0.648  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.989      ;
; 0.650  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 1.991      ;
; 0.661  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.002      ;
; 0.667  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.962      ;
; 0.670  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.476      ; 1.400      ;
; 0.698  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.203      ; 4.894      ;
; 0.698  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.203      ; 4.894      ;
; 0.700  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.087      ; 2.029      ;
; 0.706  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.503      ; 1.463      ;
; 0.710  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_3__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.004      ;
; 0.715  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck2_Z                                                                                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck3_Z                                                                          ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.010      ;
; 0.717  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.058      ;
; 0.718  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.059      ;
; 0.719  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.060      ;
; 0.720  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.061      ;
; 0.720  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.061      ;
; 0.721  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.062      ;
; 0.721  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.062      ;
; 0.736  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.077      ;
; 0.737  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.096      ; 2.075      ;
; 0.738  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.033      ;
; 0.746  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.504      ; 1.504      ;
; 0.750  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.504      ; 1.508      ;
; 0.759  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.054      ;
; 0.760  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.082      ; 2.084      ;
; 0.765  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.086      ; 2.093      ;
; 0.768  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.095      ;
; 0.780  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.503      ; 1.537      ;
; 0.813  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|rst_Z                                                        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.098      ; 2.153      ;
; 0.820  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z                                                                     ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.476      ; 1.550      ;
; 0.831  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_5__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.125      ;
; 0.850  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.191      ;
; 0.854  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.195      ;
; 0.867  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.478      ; 1.599      ;
; 0.869  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.210      ;
; 0.870  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.211      ;
; 0.876  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.203      ;
; 0.878  ; SW_USER4                                                                                                                              ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ; SW_USER4                                                                         ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.191      ; 5.311      ;
; 0.896  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.098      ; 2.236      ;
; 0.899  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.226      ;
; 0.908  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.235      ;
; 0.909  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.250      ;
; 0.909  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.204      ;
; 0.912  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.253      ;
; 0.915  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.114      ; 1.241      ;
; 0.918  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.213      ;
; 0.919  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.098      ; 2.259      ;
; 0.921  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.248      ;
; 0.929  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.270      ;
; 0.929  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                                           ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff1_Z                                                                     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.224      ;
; 0.929  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.224      ;
; 0.936  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.231      ;
; 0.939  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_1__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.234      ;
; 0.949  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_18__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.275      ;
; 0.950  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_9__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.244      ;
; 0.950  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.244      ;
; 0.958  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.253      ;
; 0.961  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|rst_Z                                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|tmp_Z                                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.256      ;
; 0.971  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.099      ; 2.312      ;
; 0.975  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.270      ;
; 0.977  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_0__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.272      ;
; 0.980  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z                                                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.275      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; -0.504 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 2.708      ;
; 0.464  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.758      ;
; 0.464  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.758      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.713  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.148      ;
; 0.743  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.037      ;
; 0.744  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.038      ;
; 0.744  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.038      ;
; 0.744  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.038      ;
; 0.745  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.039      ;
; 0.746  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.040      ;
; 0.747  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.041      ;
; 0.747  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.041      ;
; 0.747  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.041      ;
; 0.748  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.042      ;
; 0.764  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.058      ;
; 0.764  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.058      ;
; 0.765  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.059      ;
; 0.768  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.062      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 0.997  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 2.669      ;
; 1.098  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.392      ;
; 1.098  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.392      ;
; 1.099  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.393      ;
; 1.099  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.393      ;
; 1.106  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.400      ;
; 1.107  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.401      ;
; 1.107  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.401      ;
; 1.108  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.402      ;
; 1.108  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.402      ;
; 1.108  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.402      ;
; 1.109  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.403      ;
; 1.110  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.404      ;
; 1.115  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.409      ;
; 1.116  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.410      ;
; 1.116  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.410      ;
; 1.117  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.411      ;
; 1.117  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.411      ;
; 1.119  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.413      ;
; 1.229  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.523      ;
; 1.229  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.523      ;
; 1.230  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.524      ;
; 1.230  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.524      ;
; 1.238  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.532      ;
; 1.239  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.533      ;
; 1.246  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.540      ;
; 1.247  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.541      ;
; 1.247  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.541      ;
; 1.248  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.542      ;
; 1.248  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.542      ;
; 1.250  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.544      ;
; 1.251  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.000      ; 4.463      ;
; 1.255  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.549      ;
; 1.256  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.550      ;
; 1.257  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.551      ;
; 1.259  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.553      ;
; 1.261  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.871      ; 4.374      ;
; 1.369  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.663      ;
; 1.370  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.664      ;
; 1.375  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.460      ; 3.047      ;
; 1.386  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.680      ;
; 1.387  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.681      ;
; 1.388  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.682      ;
; 1.390  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.684      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.553  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.488      ;
; 1.669  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.049      ; 1.930      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.019      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.019      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.019      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.019      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.019      ;
; 1.770  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.049      ; 2.031      ;
; 1.852  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.146      ;
; 1.852  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.146      ;
; 1.952  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 2.871      ; 4.565      ;
; 1.995  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.289      ;
; 2.028  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.322      ;
; 2.028  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.322      ;
; 2.028  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.322      ;
; 2.031  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 2.325      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                               ; To Node                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.451 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.463 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.758      ;
; 0.463 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.758      ;
; 0.498 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_4__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.500 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_15__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_14__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.522 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.817      ;
; 0.522 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_0__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.818      ;
; 0.523 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.818      ;
; 0.523 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_3__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.819      ;
; 0.523 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.819      ;
; 0.524 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.819      ;
; 0.525 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_7__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.820      ;
; 0.568 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.863      ;
; 0.592 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.887      ;
; 0.599 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.894      ;
; 0.682 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_6__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.976      ;
; 0.694 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.990      ;
; 0.695 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.990      ;
; 0.695 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.991      ;
; 0.695 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.991      ;
; 0.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_24__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.991      ;
; 0.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.991      ;
; 0.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.992      ;
; 0.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_20__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.992      ;
; 0.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_16__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.992      ;
; 0.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_9__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.992      ;
; 0.697 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.993      ;
; 0.698 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_26__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.993      ;
; 0.698 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_18__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.993      ;
; 0.698 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.994      ;
; 0.709 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.003      ;
; 0.709 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_7__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.003      ;
; 0.714 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.009      ;
; 0.720 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.015      ;
; 0.720 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.015      ;
; 0.720 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.015      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.016      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.016      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.016      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.016      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.015      ;
; 0.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.017      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.017      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.017      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.017      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.016      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.017      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.016      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.016      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.016      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.018      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.018      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.017      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.017      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.017      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.017      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.018      ;
; 0.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.019      ;
; 0.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.018      ;
; 0.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.019      ;
; 0.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.019      ;
; 0.725 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.020      ;
; 0.727 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.022      ;
; 0.737 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.576      ; 1.525      ;
; 0.739 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.034      ;
; 0.740 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.035      ;
; 0.744 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.039      ;
; 0.746 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.115      ; 1.073      ;
; 0.749 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.115      ; 1.076      ;
; 0.751 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.055      ;
; 0.761 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.065      ;
; 0.778 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.082      ;
; 0.788 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.575      ; 1.575      ;
; 0.791 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.095      ;
; 0.793 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.097      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.103      ;
; 0.805 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 1.109      ;
; 0.814 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 1.117      ;
; 0.818 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.113      ;
; 0.826 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.121      ;
; 0.826 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.121      ;
; 0.827 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.122      ;
; 0.832 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.127      ;
; 0.892 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_29__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_28__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.188      ;
; 0.896 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_2__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_1__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.192      ;
; 0.899 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.195      ;
; 0.901 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.196      ;
; 0.904 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 1.200      ;
; 0.904 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_4__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_3__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.199      ;
; 0.905 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_30__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_29__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.200      ;
; 0.906 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_23__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.201      ;
; 0.908 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.203      ;
; 0.911 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.206      ;
; 0.912 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.207      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SW_USER2'                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.497 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.049      ; 0.758      ;
; 0.916 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.184      ;
; 1.143 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.411      ;
; 1.145 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.413      ;
; 1.150 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.418      ;
; 1.155 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.423      ;
; 1.155 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.423      ;
; 1.187 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.455      ;
; 1.187 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.455      ;
; 1.188 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.456      ;
; 1.275 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.543      ;
; 1.277 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.545      ;
; 1.327 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.595      ;
; 1.328 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.596      ;
; 1.448 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.716      ;
; 1.448 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.716      ;
; 1.449 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.717      ;
; 1.468 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.736      ;
; 1.471 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.739      ;
; 1.476 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.744      ;
; 1.481 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.749      ;
; 1.481 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.749      ;
; 1.529 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.797      ;
; 1.531 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.799      ;
; 1.540 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.808      ;
; 1.542 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.810      ;
; 1.558 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.826      ;
; 1.559 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.827      ;
; 1.559 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.827      ;
; 1.560 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.828      ;
; 1.568 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.836      ;
; 1.569 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.837      ;
; 1.570 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.838      ;
; 1.580 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.848      ;
; 1.580 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.848      ;
; 1.581 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.849      ;
; 1.581 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.849      ;
; 1.601 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.869      ;
; 1.603 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.871      ;
; 1.652 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.920      ;
; 1.667 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.935      ;
; 1.668 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.936      ;
; 1.682 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.950      ;
; 1.698 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.966      ;
; 1.700 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.968      ;
; 1.703 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.971      ;
; 1.722 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 1.990      ;
; 1.859 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.127      ;
; 1.861 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.129      ;
; 1.962 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.230      ;
; 1.962 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.230      ;
; 1.963 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.231      ;
; 1.967 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.235      ;
; 1.969 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.237      ;
; 2.228 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.496      ;
; 2.236 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.504      ;
; 2.236 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.056      ; 2.504      ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_BRD'                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.758 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.053      ;
; 0.759 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.054      ;
; 0.762 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.057      ;
; 0.763 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.058      ;
; 0.763 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.058      ;
; 0.764 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.059      ;
; 0.769 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.063      ;
; 0.770 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.064      ;
; 0.779 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.073      ;
; 0.781 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.075      ;
; 0.781 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.075      ;
; 0.786 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.080      ;
; 0.938 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.233      ;
; 0.938 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.232      ;
; 0.950 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.245      ;
; 0.959 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.254      ;
; 0.959 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.254      ;
; 0.962 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.257      ;
; 0.963 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.258      ;
; 0.968 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.262      ;
; 0.972 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.267      ;
; 0.972 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.266      ;
; 0.973 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.267      ;
; 0.978 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.272      ;
; 0.991 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.286      ;
; 0.992 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.286      ;
; 1.113 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.408      ;
; 1.114 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.409      ;
; 1.123 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.418      ;
; 1.124 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.419      ;
; 1.124 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.419      ;
; 1.124 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.418      ;
; 1.131 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.425      ;
; 1.132 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.427      ;
; 1.133 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.428      ;
; 1.133 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.428      ;
; 1.140 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.434      ;
; 1.147 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.441      ;
; 1.156 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.450      ;
; 1.165 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.104      ; 1.481      ;
; 1.166 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.103      ; 1.481      ;
; 1.196 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.490      ;
; 1.244 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.539      ;
; 1.245 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.540      ;
; 1.253 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.548      ;
; 1.254 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.549      ;
; 1.255 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.549      ;
; 1.264 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.559      ;
; 1.264 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.559      ;
; 1.264 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.558      ;
; 1.271 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.565      ;
; 1.273 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.568      ;
; 1.273 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.568      ;
; 1.280 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.574      ;
; 1.287 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.581      ;
; 1.292 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.587      ;
; 1.293 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.587      ;
; 1.296 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.591      ;
; 1.296 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.590      ;
; 1.305 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.600      ;
; 1.308 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.603      ;
; 1.308 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.603      ;
; 1.312 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.102      ; 1.626      ;
; 1.317 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.612      ;
; 1.319 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.613      ;
; 1.321 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.615      ;
; 1.323 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.617      ;
; 1.326 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.621      ;
; 1.327 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.621      ;
; 1.328 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.622      ;
; 1.329 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.624      ;
; 1.329 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.624      ;
; 1.333 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.628      ;
; 1.343 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.637      ;
; 1.346 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.641      ;
; 1.348 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.642      ;
; 1.350 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.081      ; 1.643      ;
; 1.383 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.678      ;
; 1.384 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.679      ;
; 1.384 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.678      ;
; 1.385 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.680      ;
; 1.390 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.081      ; 1.683      ;
; 1.391 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.686      ;
; 1.392 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.081      ; 1.685      ;
; 1.393 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.688      ;
; 1.394 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.689      ;
; 1.395 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.689      ;
; 1.397 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.692      ;
; 1.398 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.693      ;
; 1.398 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.692      ;
; 1.401 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.081      ; 1.694      ;
; 1.404 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.699      ;
; 1.404 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.699      ;
; 1.404 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.698      ;
; 1.406 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.700      ;
; 1.408 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.702      ;
; 1.411 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.705      ;
; 1.411 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.705      ;
; 1.413 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.083      ; 1.708      ;
; 1.420 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.082      ; 1.714      ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.696 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.580      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.631 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.526      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.559 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.443      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.389      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.383 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.267      ;
; -2.345 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.240      ;
; -2.345 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.240      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.213      ;
; -2.208 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.103      ;
; -2.208 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.103      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.178 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 3.062      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 3.008      ;
; -2.032 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 2.927      ;
; -2.032 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 2.927      ;
; -1.827 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 2.722      ;
; -1.827 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.106     ; 2.722      ;
; -1.364 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.095     ; 1.770      ;
; -1.364 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.095     ; 1.770      ;
; -1.364 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.095     ; 1.770      ;
; -1.364 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.095     ; 1.770      ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                        ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -2.514 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.190      ; 4.195      ;
; -2.023 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.190      ; 4.204      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.933 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.000      ; 5.424      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.859 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 4.003      ; 5.353      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.685 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.000      ; 5.676      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; -0.365 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 4.003      ; 5.359      ;
; 0.319  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 2.733      ; 2.905      ;
; 0.724  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 2.733      ; 3.000      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.723 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.506      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.586 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.369      ;
; -1.467 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.240      ;
; -1.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.784      ; 3.225      ;
; -1.446 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.219      ;
; -1.446 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.219      ;
; -1.421 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.195      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.410 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 3.193      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.181      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.181      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.391 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.175      ;
; -1.330 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.103      ;
; -1.313 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.784      ; 3.088      ;
; -1.309 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.082      ;
; -1.309 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 3.082      ;
; -1.284 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.058      ;
; -1.270 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.044      ;
; -1.270 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 3.044      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 3.038      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.792      ; 2.988      ;
; -1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.927      ;
; -1.137 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.784      ; 2.912      ;
; -1.133 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.906      ;
; -1.133 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.906      ;
; -1.108 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.882      ;
; -1.094 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.868      ;
; -1.094 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.868      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -1.078 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.862      ;
; -0.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.722      ;
; -0.932 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.784      ; 2.707      ;
; -0.928 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.701      ;
; -0.928 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.782      ; 2.701      ;
; -0.903 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.677      ;
; -0.889 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.663      ;
; -0.889 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.783      ; 2.663      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.873 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.793      ; 2.657      ;
; -0.794 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.580      ;
; -0.794 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.580      ;
; -0.628 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.414      ;
; -0.628 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.414      ;
; -0.452 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.238      ;
; -0.452 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.238      ;
; -0.275 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.061      ;
; -0.275 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.795      ; 2.061      ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                         ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.208 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.871      ; 2.905      ;
; 0.198  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 2.871      ; 2.811      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 0.734  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.193      ; 5.169      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.042  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 4.190      ; 5.474      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.221  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.193      ; 5.156      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 1.297  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 4.190      ; 5.229      ;
; 2.557  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.262      ; 4.061      ;
; 3.046  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.262      ; 4.050      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; 0.570 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 1.909      ;
; 0.570 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 1.909      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.025      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.025      ;
; 0.876 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.215      ;
; 0.876 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.215      ;
; 1.067 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.406      ;
; 1.067 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.097      ; 2.406      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.122 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.458      ;
; 1.132 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.458      ;
; 1.132 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.458      ;
; 1.141 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.467      ;
; 1.189 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.516      ;
; 1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.530      ;
; 1.205 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.530      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.209 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.545      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.545      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.545      ;
; 1.221 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.546      ;
; 1.228 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.554      ;
; 1.276 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.603      ;
; 1.292 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.617      ;
; 1.292 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.617      ;
; 1.308 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.633      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.397 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.733      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.735      ;
; 1.409 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.735      ;
; 1.409 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.735      ;
; 1.418 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.744      ;
; 1.466 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 2.793      ;
; 1.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.807      ;
; 1.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.807      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.484 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.820      ;
; 1.498 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 2.823      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.622 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 2.958      ;
; 1.632 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.958      ;
; 1.632 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.958      ;
; 1.641 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.084      ; 2.967      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.674 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.010      ;
; 1.689 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.085      ; 3.016      ;
; 1.705 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 3.030      ;
; 1.705 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 3.030      ;
; 1.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.083      ; 3.046      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
; 1.897 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.094      ; 3.233      ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.847 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.070      ; 1.649      ;
; 1.847 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.070      ; 1.649      ;
; 1.847 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.070      ; 1.649      ;
; 1.847 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.070      ; 1.649      ;
; 2.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.546      ;
; 2.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.546      ;
; 2.321 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.633      ;
; 2.321 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.633      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.449 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.762      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.504 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.805      ;
; 2.511 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.823      ;
; 2.511 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 2.823      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.536 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 2.849      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.591 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.892      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.039      ;
; 2.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 3.046      ;
; 2.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 3.046      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.781 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.082      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 2.949 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 3.262      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
; 3.004 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 3.305      ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                          ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                                                                            ; Clock Edge ; Target                                                                                                           ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_we_reg       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_0__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_1__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_2__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_3__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_4__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_5__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_6__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_7__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_10__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_2__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_8__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z                                                         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_0__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_10__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_11__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_12__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_13__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_14__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_15__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_16__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_17__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_18__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_19__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_20__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_7__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_8__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_9__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z                                   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_0__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_3__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_0__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_2__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_4__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_6__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_0__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_15__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                                                                                       ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                                                                                        ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                                                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_0__Z ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_19__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_20__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_17__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_18__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_19__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_20__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_3__Z          ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK_BRD ; Rise       ; CLK_BRD                                                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.236  ; 0.456        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; 0.247  ; 0.467        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; 0.256  ; 0.476        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; 0.257  ; 0.477        ; 0.220          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.332  ; 0.520        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; 0.333  ; 0.521        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; 0.334  ; 0.522        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; 0.342  ; 0.530        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; 0.352  ; 0.540        ; 0.188          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~input|o                                                                  ;
; 0.465  ; 0.465        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|inclk[0]                                                    ;
; 0.465  ; 0.465        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|outclk                                                      ;
; 0.472  ; 0.472        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|clk                                                 ;
; 0.473  ; 0.473        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_10|ff1|dffs[0]|clk                                                      ;
; 0.473  ; 0.473        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_11|ff1|dffs[0]|clk                                                      ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER3'                                                                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER3 ; Rise       ; SW_USER3                                                                                           ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -0.080 ; 0.140        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; -0.079 ; 0.141        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -0.079 ; 0.141        ; 0.220          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.189  ; 0.189        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
; 0.190  ; 0.190        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.190  ; 0.190        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
; 0.198  ; 0.198        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.198  ; 0.198        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.329  ; 0.329        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.648  ; 0.648        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; 0.655  ; 0.843        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; 0.656  ; 0.844        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; 0.656  ; 0.844        ; 0.188          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; 0.661  ; 0.661        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
; 0.787  ; 0.787        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.787  ; 0.787        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.795  ; 0.795        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
; 0.796  ; 0.796        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.796  ; 0.796        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER2'                                                                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER2 ; Rise       ; SW_USER2                                                                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.200  ; 0.420        ; 0.220          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.389  ; 0.577        ; 0.188          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.469  ; 0.469        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.529  ; 0.529        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SW_USER4'                                                                                                                   ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                              ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER4 ; Rise       ; SW_USER4                                                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.108  ; 0.328        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.109  ; 0.329        ; 0.220          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.377  ; 0.377        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.378  ; 0.378        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.385  ; 0.385        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.385  ; 0.385        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.477  ; 0.477        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
; 0.479  ; 0.667        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.480  ; 0.668        ; 0.188          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.490  ; 0.490        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.508  ; 0.508        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
; 0.521  ; 0.521        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.612  ; 0.612        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.612  ; 0.612        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 0.619  ; 0.619        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.620  ; 0.620        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.179  ; 0.399        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.182  ; 0.402        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.241  ; 0.461        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.254  ; 0.474        ; 0.220          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.337  ; 0.525        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.350  ; 0.538        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.407  ; 0.595        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.410  ; 0.598        ; 0.188          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.448  ; 0.448        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.451  ; 0.451        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.476  ; 0.476        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.490  ; 0.490        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.510  ; 0.510        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.522  ; 0.522        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.547  ; 0.547        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.550  ; 0.550        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.047  ; 0.392  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.852  ; 1.770  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 1.617  ; 1.822  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.297  ; 3.296  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; 3.662  ; 3.895  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; 3.541  ; 3.793  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; 2.377  ; 2.645  ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 0.658  ; 1.138  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; -1.008 ; -0.917 ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; -0.569 ; -0.216 ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.617  ; 1.068  ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; -0.346 ; 0.002  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; -1.042 ; -0.693 ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; -0.254 ; 0.212  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.658  ; 1.088  ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.598  ; 1.138  ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; -0.772 ; -0.462 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                          ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.558  ; 0.257  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.908 ; -1.108 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.743 ; -1.083 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -2.479 ; -2.575 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; -2.233 ; -2.519 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; -2.903 ; -3.211 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; -1.793 ; -2.023 ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 1.837  ; 1.738  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; 1.837  ; 1.738  ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; 1.306  ; 0.965  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.170  ; -0.266 ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; 1.092  ; 0.756  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; 1.760  ; 1.422  ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; 1.002  ; 0.554  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.130  ; -0.284 ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.188  ; -0.334 ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; 1.580  ; 1.350  ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                               ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 11.331 ; 11.060 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 11.331 ; 11.060 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.149  ; 7.059  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.149  ; 7.059  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.514  ; 9.301  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.514  ; 9.301  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.815  ; 7.588  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 18.377 ; 17.887 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 9.044  ; 8.594  ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 9.044  ; 8.594  ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 14.175 ; 13.887 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 13.158 ; 12.885 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 14.175 ; 13.887 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 11.945 ; 11.845 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 13.086 ; 12.948 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 17.499 ; 17.112 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 16.366 ; 15.842 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 15.796 ; 15.422 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 16.675 ; 16.608 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 17.499 ; 17.112 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 14.410 ; 13.992 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 15.164 ; 14.732 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 12.124 ; 12.046 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 12.987 ; 12.875 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 18.826 ; 18.102 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 17.495 ; 17.144 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 16.281 ; 15.928 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 18.278 ; 17.822 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 18.379 ; 17.745 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 17.129 ; 16.670 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 18.826 ; 18.102 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 18.548 ; 18.013 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 13.918 ; 13.669 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.437  ; 8.291  ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 9.103  ; 8.820  ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.437  ; 8.291  ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 9.103  ; 8.820  ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 16.976 ; 16.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 14.495 ; 14.388 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 16.545 ; 16.145 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 15.764 ; 15.450 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 16.976 ; 16.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 14.304 ; 14.037 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 16.037 ; 15.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 15.759 ; 15.412 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 14.687 ; 14.354 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 13.392 ; 13.047 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 13.392 ; 13.047 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 13.064 ; 12.754 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 11.953 ; 11.765 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 11.985 ; 11.756 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                       ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.965 ; 10.701 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.965 ; 10.701 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.961  ; 6.872  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.961  ; 6.872  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.599  ; 7.378  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.227  ; 9.021  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.599  ; 7.378  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 9.964  ; 9.797  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 8.820  ; 8.389  ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 8.820  ; 8.389  ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 8.820  ; 8.389  ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 12.751 ; 12.484 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 13.726 ; 13.446 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 8.820  ; 8.389  ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 12.667 ; 12.523 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 11.765 ; 11.688 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 15.839 ; 15.333 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 15.257 ; 14.870 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 16.151 ; 16.071 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 16.889 ; 16.496 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 13.919 ; 13.489 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 14.639 ; 14.201 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 11.765 ; 11.688 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 12.594 ; 12.485 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 13.485 ; 13.246 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 16.920 ; 16.581 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 15.757 ; 15.415 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 17.673 ; 17.235 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 17.770 ; 17.160 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 16.563 ; 16.119 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 18.191 ; 17.492 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 17.928 ; 17.411 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 13.485 ; 13.246 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 8.244  ; 8.100  ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.813  ; 8.868  ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.244  ; 8.100  ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 8.882  ; 8.606  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.665  ; 9.247  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.882  ; 8.606  ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 8.244  ; 8.100  ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.813  ; 8.868  ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.244  ; 8.100  ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 8.882  ; 8.606  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.665  ; 9.247  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.882  ; 8.606  ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 13.854 ; 13.595 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 14.045 ; 13.940 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 15.993 ; 15.599 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 15.264 ; 14.961 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 16.427 ; 15.969 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 13.854 ; 13.595 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 15.519 ; 14.999 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 15.255 ; 14.919 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 14.167 ; 13.839 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 11.598 ; 11.406 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 12.979 ; 12.645 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 12.665 ; 12.364 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 11.598 ; 11.415 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 11.630 ; 11.406 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF     ; FR     ; FF ;
+------------+-------------+----+--------+--------+----+
; HA[12]     ; LED_G[0]    ;    ; 11.669 ; 12.227 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 10.660 ; 11.085 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 11.848 ; 11.963 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 12.100 ; 12.612 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 9.210  ; 9.655  ;    ;
; HA[17]     ; LED_G[5]    ;    ; 10.149 ; 10.738 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 8.465  ; 8.732  ;    ;
; HA[19]     ; LED_G[7]    ;    ; 8.032  ; 8.384  ;    ;
+------------+-------------+----+--------+--------+----+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF     ; FR     ; FF ;
+------------+-------------+----+--------+--------+----+
; HA[12]     ; LED_G[0]    ;    ; 11.341 ; 11.875 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 10.371 ; 10.778 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 11.573 ; 11.677 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 11.755 ; 12.246 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 8.971  ; 9.398  ;    ;
; HA[17]     ; LED_G[5]    ;    ; 9.872  ; 10.437 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 8.264  ; 8.519  ;    ;
; HA[19]     ; LED_G[7]    ;    ; 7.851  ; 8.186  ;    ;
+------------+-------------+----+--------+--------+----+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                               ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                       ; Note                                                          ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
; 93.32 MHz  ; 93.32 MHz       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;                                                               ;
; 178.79 MHz ; 178.79 MHz      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;                                                               ;
; 196.89 MHz ; 196.89 MHz      ; JTAG_NEXUS_TCK                                                                   ;                                                               ;
; 204.12 MHz ; 204.12 MHz      ; CLK_BRD                                                                          ;                                                               ;
; 374.25 MHz ; 250.0 MHz       ; SW_USER4                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
; 375.94 MHz ; 250.0 MHz       ; SW_USER2                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
; 378.93 MHz ; 250.0 MHz       ; SW_USER3                                                                         ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+----------------------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                        ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -8.977 ; -559.773      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -4.593 ; -34.954       ;
; JTAG_NEXUS_TCK                                                                   ; -4.079 ; -796.833      ;
; CLK_BRD                                                                          ; -3.899 ; -98.876       ;
; SW_USER4                                                                         ; -1.672 ; -11.157       ;
; SW_USER2                                                                         ; -1.660 ; -10.877       ;
; SW_USER3                                                                         ; -1.639 ; -12.076       ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                         ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; SW_USER3                                                                         ; -1.557 ; -1.557        ;
; SW_USER4                                                                         ; -1.269 ; -9.760        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.517 ; -0.930        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.492 ; -2.952        ;
; JTAG_NEXUS_TCK                                                                   ; 0.399  ; 0.000         ;
; SW_USER2                                                                         ; 0.445  ; 0.000         ;
; CLK_BRD                                                                          ; 0.703  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                     ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; JTAG_NEXUS_TCK                                                                   ; -2.485 ; -55.544       ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -2.260 ; -12.480       ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -1.574 ; -27.143       ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                      ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.163 ; -0.163        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.494  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                   ; 1.701  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                          ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -3.201 ; -245.105      ;
; JTAG_NEXUS_TCK                                                                   ; -3.000 ; -374.750      ;
; CLK_BRD                                                                          ; -3.000 ; -49.097       ;
; SW_USER3                                                                         ; -3.000 ; -17.508       ;
; SW_USER2                                                                         ; -3.000 ; -14.896       ;
; SW_USER4                                                                         ; -3.000 ; -14.896       ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.487 ; -23.792       ;
+----------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                            ; To Node                                                                   ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -8.977 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.899      ;
; -8.977 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.899      ;
; -8.869 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.791      ;
; -8.869 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.791      ;
; -8.835 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.757      ;
; -8.835 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.757      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.724 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.646      ;
; -8.624 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.554      ;
; -8.624 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.554      ;
; -8.624 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.554      ;
; -8.624 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.554      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.616 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.538      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.582 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.504      ;
; -8.516 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.446      ;
; -8.516 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.446      ;
; -8.516 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.446      ;
; -8.516 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.446      ;
; -8.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.412      ;
; -8.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.412      ;
; -8.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.412      ;
; -8.482 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 9.412      ;
; -8.312 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.234      ;
; -8.312 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 9.234      ;
; -8.139 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.884      ;
; -8.139 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.884      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 9.034      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.096 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.841      ;
; -8.089 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.754      ; 9.835      ;
; -8.089 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.754      ; 9.835      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.072 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.357      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -8.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.080     ; 8.981      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.987 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.908      ;
; -7.968 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.713      ;
; -7.968 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.753      ; 9.713      ;
; -7.959 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 8.889      ;
; -7.959 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 8.889      ;
; -7.959 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 8.889      ;
; -7.959 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 8.889      ;
; -7.903 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.188      ;
; -7.903 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.293      ; 9.188      ;
; -7.885 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.754      ; 9.631      ;
; -7.885 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.754      ; 9.631      ;
; -7.848 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.769      ;
; -7.848 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.081     ; 8.769      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -4.593 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.833      ;
; -4.516 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.756      ;
; -4.501 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.741      ;
; -4.467 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.707      ;
; -4.377 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.617      ;
; -4.339 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.579      ;
; -4.326 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -2.762     ; 2.566      ;
; -3.276 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 3.010      ;
; -3.195 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.929      ;
; -3.185 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.919      ;
; -3.150 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.884      ;
; -3.068 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.802      ;
; -3.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.758      ;
; -2.936 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.268     ; 2.670      ;
; -2.569 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.116      ; 4.177      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.474 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 6.670      ;
; -2.203 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.116      ; 4.311      ;
; -1.875 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.044     ; 2.833      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.834 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 6.530      ;
; -1.771 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.044     ; 2.729      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.639 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.569      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.636 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.566      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.514 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.444      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.477 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.407      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.459 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.388      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.354 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.284      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.342 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.272      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.324 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.253      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.309 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.238      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.217 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.072     ; 2.147      ;
; -1.187 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.116      ;
; -1.187 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 2.116      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                               ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                     ; To Node                                                                                                                                ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -4.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.979      ;
; -4.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.979      ;
; -4.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.979      ;
; -4.017 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.935      ;
; -4.017 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.935      ;
; -4.017 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.935      ;
; -4.017 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.935      ;
; -4.014 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.914      ;
; -4.014 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.914      ;
; -4.014 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.914      ;
; -4.013 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.931      ;
; -4.013 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.931      ;
; -4.013 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.931      ;
; -4.013 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.931      ;
; -3.947 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.866      ;
; -3.943 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.862      ;
; -3.942 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.870      ;
; -3.942 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.870      ;
; -3.942 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.870      ;
; -3.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.855      ;
; -3.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.855      ;
; -3.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.855      ;
; -3.923 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.851      ;
; -3.923 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.851      ;
; -3.923 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.851      ;
; -3.919 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.819      ;
; -3.919 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.819      ;
; -3.919 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.819      ;
; -3.899 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.817      ;
; -3.899 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.817      ;
; -3.899 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.817      ;
; -3.899 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.817      ;
; -3.877 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.777      ;
; -3.877 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.777      ;
; -3.877 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.777      ;
; -3.877 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.777      ;
; -3.877 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.777      ;
; -3.829 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 4.748      ;
; -3.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.718      ;
; -3.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.718      ;
; -3.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.718      ;
; -3.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 4.718      ;
; -3.809 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.737      ;
; -3.809 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.737      ;
; -3.809 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 4.737      ;
; -3.785 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.684      ;
; -3.785 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.684      ;
; -3.785 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.684      ;
; -3.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.673      ;
; -3.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.673      ;
; -3.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_5__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.673      ;
; -3.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.673      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.665      ;
; -3.758 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.657      ;
; -3.758 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.657      ;
; -3.758 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.657      ;
; -3.755 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.654      ;
; -3.755 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.654      ;
; -3.755 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.654      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_0__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.747 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.647      ;
; -3.741 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 4.649      ;
; -3.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.652      ;
; -3.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.652      ;
; -3.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.652      ;
; -3.734 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.652      ;
; -3.725 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.643      ;
; -3.721 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 4.639      ;
; -3.717 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.616      ;
; -3.717 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.616      ;
; -3.717 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.616      ;
; -3.717 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 4.616      ;
; -3.710 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.610      ;
; -3.710 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.610      ;
; -3.710 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.610      ;
; -3.710 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.610      ;
; -3.710 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.610      ;
; -3.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.608      ;
; -3.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.608      ;
; -3.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_5__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.608      ;
; -3.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.608      ;
; -3.700 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.600      ;
; -3.700 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.600      ;
; -3.700 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.102     ; 4.600      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -3.899 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.826      ;
; -3.860 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.787      ;
; -3.801 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.728      ;
; -3.792 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.720      ;
; -3.773 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.700      ;
; -3.772 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.700      ;
; -3.769 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.697      ;
; -3.762 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.689      ;
; -3.743 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.670      ;
; -3.734 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.661      ;
; -3.734 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.661      ;
; -3.704 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.631      ;
; -3.702 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.629      ;
; -3.695 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.622      ;
; -3.685 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.612      ;
; -3.675 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.602      ;
; -3.666 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.594      ;
; -3.663 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.590      ;
; -3.647 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.574      ;
; -3.646 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.573      ;
; -3.646 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.574      ;
; -3.643 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.571      ;
; -3.636 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.563      ;
; -3.627 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.555      ;
; -3.617 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.544      ;
; -3.608 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.535      ;
; -3.608 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.535      ;
; -3.607 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.535      ;
; -3.604 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.532      ;
; -3.578 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.505      ;
; -3.576 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.503      ;
; -3.569 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.496      ;
; -3.567 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.494      ;
; -3.559 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.486      ;
; -3.549 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.476      ;
; -3.546 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.473      ;
; -3.540 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.468      ;
; -3.537 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.464      ;
; -3.528 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.455      ;
; -3.521 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.448      ;
; -3.520 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.447      ;
; -3.520 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.448      ;
; -3.517 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.445      ;
; -3.510 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.437      ;
; -3.507 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.434      ;
; -3.501 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.429      ;
; -3.491 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.418      ;
; -3.491 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.419      ;
; -3.482 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.409      ;
; -3.482 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.409      ;
; -3.481 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.409      ;
; -3.478 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.406      ;
; -3.452 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.379      ;
; -3.450 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.377      ;
; -3.449 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.377      ;
; -3.443 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.370      ;
; -3.442 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.370      ;
; -3.441 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.368      ;
; -3.436 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.363      ;
; -3.433 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.360      ;
; -3.423 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.350      ;
; -3.420 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.347      ;
; -3.414 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.341      ;
; -3.414 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.342      ;
; -3.411 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.338      ;
; -3.402 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.329      ;
; -3.401 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.328      ;
; -3.395 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.322      ;
; -3.394 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.321      ;
; -3.394 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.322      ;
; -3.393 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.320      ;
; -3.392 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.319      ;
; -3.391 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.319      ;
; -3.384 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.311      ;
; -3.381 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.308      ;
; -3.375 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.302      ;
; -3.375 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.303      ;
; -3.365 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.292      ;
; -3.365 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.293      ;
; -3.356 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.283      ;
; -3.356 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.283      ;
; -3.355 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.283      ;
; -3.354 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.281      ;
; -3.353 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.280      ;
; -3.352 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.280      ;
; -3.326 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.253      ;
; -3.326 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.254      ;
; -3.324 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.251      ;
; -3.323 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.251      ;
; -3.317 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.244      ;
; -3.316 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.244      ;
; -3.316 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.244      ;
; -3.315 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.242      ;
; -3.310 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.237      ;
; -3.307 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.234      ;
; -3.300 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.228      ;
; -3.297 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.224      ;
; -3.294 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.221      ;
; -3.288 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.075     ; 4.215      ;
; -3.288 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.074     ; 4.216      ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SW_USER4'                                                                                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.672 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.602      ;
; -1.664 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.594      ;
; -1.655 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.585      ;
; -1.582 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.512      ;
; -1.581 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.511      ;
; -1.538 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.468      ;
; -1.529 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.459      ;
; -1.499 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.429      ;
; -1.490 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.420      ;
; -1.454 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.384      ;
; -1.447 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.377      ;
; -1.417 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.347      ;
; -1.408 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.338      ;
; -1.405 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.335      ;
; -1.396 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.326      ;
; -1.372 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.302      ;
; -1.314 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.244      ;
; -1.310 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.240      ;
; -1.300 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.230      ;
; -1.291 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.221      ;
; -1.246 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.176      ;
; -1.184 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.114      ;
; -1.174 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.104      ;
; -1.173 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.103      ;
; -1.167 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.097      ;
; -1.166 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.096      ;
; -1.162 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.092      ;
; -1.152 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.082      ;
; -1.151 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.081      ;
; -1.148 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.078      ;
; -1.147 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.077      ;
; -1.121 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.051      ;
; -1.120 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.050      ;
; -1.118 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.048      ;
; -1.118 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.048      ;
; -1.117 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.047      ;
; -1.107 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 2.037      ;
; -1.003 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.933      ;
; -0.999 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.929      ;
; -0.976 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.906      ;
; -0.972 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.902      ;
; -0.971 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.901      ;
; -0.971 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.901      ;
; -0.970 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.900      ;
; -0.969 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.899      ;
; -0.943 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.873      ;
; -0.913 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.843      ;
; -0.878 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.808      ;
; -0.874 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.804      ;
; -0.847 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.777      ;
; -0.846 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.776      ;
; -0.845 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.775      ;
; -0.844 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.774      ;
; -0.661 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.591      ;
; -0.626 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.556      ;
; -0.502 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.073     ; 1.431      ;
; -0.365 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.072     ; 1.295      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.169      ; 4.362      ;
; 0.357  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 4.168      ; 4.303      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.269  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.911      ; 6.124      ;
; 1.322  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 6.910      ; 6.070      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.377  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.911      ; 6.516      ;
; 1.435  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 6.910      ; 6.457      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SW_USER2'                                                                                                                                                                                                                                                     ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.660 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.632      ;
; -1.628 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.600      ;
; -1.588 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.560      ;
; -1.585 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.557      ;
; -1.582 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.554      ;
; -1.577 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.549      ;
; -1.575 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.547      ;
; -1.547 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.519      ;
; -1.536 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.508      ;
; -1.452 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.424      ;
; -1.441 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.413      ;
; -1.365 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.337      ;
; -1.365 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.337      ;
; -1.354 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.326      ;
; -1.337 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.309      ;
; -1.331 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.303      ;
; -1.320 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.292      ;
; -1.288 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.260      ;
; -1.287 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.259      ;
; -1.286 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.258      ;
; -1.266 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.238      ;
; -1.263 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.235      ;
; -1.258 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.230      ;
; -1.256 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.228      ;
; -1.252 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.224      ;
; -1.241 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.213      ;
; -1.241 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.213      ;
; -1.240 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.212      ;
; -1.240 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.212      ;
; -1.229 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.201      ;
; -1.192 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.164      ;
; -1.190 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.162      ;
; -1.161 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.133      ;
; -1.158 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.130      ;
; -1.151 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.123      ;
; -1.120 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.092      ;
; -1.117 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.089      ;
; -1.116 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.088      ;
; -1.115 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.087      ;
; -1.103 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.075      ;
; -1.070 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.042      ;
; -1.067 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 2.039      ;
; -0.975 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.947      ;
; -0.973 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.945      ;
; -0.969 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.941      ;
; -0.968 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.940      ;
; -0.967 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.939      ;
; -0.878 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.850      ;
; -0.864 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.836      ;
; -0.863 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.835      ;
; -0.862 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.834      ;
; -0.845 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.817      ;
; -0.843 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.815      ;
; -0.841 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.813      ;
; -0.773 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.745      ;
; -0.772 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.050     ; 1.744      ;
; 0.208  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.044     ; 0.770      ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SW_USER3'                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.639 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.568      ;
; -1.610 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.539      ;
; -1.523 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.452      ;
; -1.512 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.441      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.491 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.420      ;
; -1.480 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.409      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.453 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.382      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.438 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.367      ;
; -1.419 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.348      ;
; -1.384 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.313      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.344 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.273      ;
; -1.285 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.214      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.284 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.213      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.278 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.207      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.108      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.176 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 2.105      ;
; -1.031 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 1.960      ;
; 0.159  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.073     ; 0.770      ;
; 0.972  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.822      ;
; 1.102  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.692      ;
; 1.108  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.686      ;
; 1.152  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.642      ;
; 1.200  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.594      ;
; 1.247  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.547      ;
; 1.261  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.533      ;
; 1.343  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 4.302      ; 3.451      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SW_USER3'                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.557 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.810      ;
; -1.545 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.822      ;
; -1.526 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.841      ;
; -1.521 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.846      ;
; -1.494 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.873      ;
; -1.446 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.921      ;
; -1.431 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.936      ;
; -1.387 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 4.642      ; 2.980      ;
; 0.416  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.684      ;
; 0.708  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.976      ;
; 0.716  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.984      ;
; 0.718  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.986      ;
; 0.718  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.986      ;
; 0.718  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.986      ;
; 0.720  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 0.988      ;
; 0.740  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.008      ;
; 0.900  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.168      ;
; 1.032  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.300      ;
; 1.035  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.303      ;
; 1.039  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.307      ;
; 1.040  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.308      ;
; 1.042  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.310      ;
; 1.042  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.310      ;
; 1.050  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.318      ;
; 1.054  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.322      ;
; 1.055  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.323      ;
; 1.139  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.407      ;
; 1.139  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.407      ;
; 1.161  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.429      ;
; 1.162  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.430      ;
; 1.164  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.432      ;
; 1.164  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.432      ;
; 1.176  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.444      ;
; 1.177  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.445      ;
; 1.204  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.472      ;
; 1.261  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.529      ;
; 1.284  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.552      ;
; 1.286  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.554      ;
; 1.299  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.567      ;
; 1.305  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.573      ;
; 1.326  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.594      ;
; 1.419  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.687      ;
; 1.427  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.695      ;
; 1.448  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.716      ;
; 1.549  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.817      ;
; 1.585  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.853      ;
; 1.676  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.944      ;
; 1.689  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 1.957      ;
; 1.760  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.028      ;
; 1.760  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.028      ;
; 1.764  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.032      ;
; 1.764  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.032      ;
; 1.764  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.032      ;
; 1.764  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.032      ;
; 1.768  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.036      ;
; 1.797  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.065      ;
; 1.800  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.068      ;
; 1.852  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.120      ;
; 1.852  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.120      ;
; 1.852  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.120      ;
; 1.919  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.187      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.984  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.252      ;
; 1.987  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.255      ;
; 1.994  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.262      ;
; 1.994  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.262      ;
; 1.994  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.262      ;
; 1.994  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.262      ;
; 1.994  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.073      ; 2.262      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SW_USER4'                                                                                                                                                                                                                                                                                           ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.269 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.148      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.213 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 7.182      ; 6.204      ;
; -1.094 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.823      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -1.042 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 7.182      ; 5.875      ;
; -0.432 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.862      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; -0.380 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 4.569      ; 3.914      ;
; 0.881  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.148      ;
; 0.884  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.151      ;
; 1.065  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.333      ;
; 1.086  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.353      ;
; 1.086  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.353      ;
; 1.089  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.356      ;
; 1.089  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.356      ;
; 1.112  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.379      ;
; 1.117  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.384      ;
; 1.118  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.385      ;
; 1.119  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.386      ;
; 1.169  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.436      ;
; 1.172  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.439      ;
; 1.186  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.453      ;
; 1.189  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.456      ;
; 1.218  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.485      ;
; 1.237  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.505      ;
; 1.240  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.508      ;
; 1.270  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.537      ;
; 1.271  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.538      ;
; 1.272  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.539      ;
; 1.276  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.543      ;
; 1.347  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.614      ;
; 1.349  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.616      ;
; 1.379  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.646      ;
; 1.383  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.650      ;
; 1.400  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.667      ;
; 1.400  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.667      ;
; 1.405  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.672      ;
; 1.405  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.672      ;
; 1.405  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.672      ;
; 1.406  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.673      ;
; 1.406  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.673      ;
; 1.407  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.674      ;
; 1.410  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.677      ;
; 1.411  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.678      ;
; 1.417  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.684      ;
; 1.417  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.684      ;
; 1.422  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.689      ;
; 1.424  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.691      ;
; 1.476  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.744      ;
; 1.476  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.744      ;
; 1.480  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.748      ;
; 1.481  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.749      ;
; 1.481  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.748      ;
; 1.482  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.073      ; 1.750      ;
; 1.483  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.750      ;
; 1.490  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.757      ;
; 1.522  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.789      ;
; 1.530  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.797      ;
; 1.555  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.822      ;
; 1.558  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.825      ;
; 1.560  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.827      ;
; 1.631  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.898      ;
; 1.633  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.900      ;
; 1.634  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.901      ;
; 1.636  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.072      ; 1.903      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                             ; To Node                                                                                                          ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -0.517 ; JTAG_NEXUS_TCK                                                                                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck1_Z                                                                          ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.901      ; 3.609      ;
; -0.387 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.779      ; 2.607      ;
; -0.015 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.895      ; 4.335      ;
; -0.011 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.895      ; 4.319      ;
; 0.029  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.906      ; 4.370      ;
; 0.061  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.895      ; 3.911      ;
; 0.077  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.906      ; 3.938      ;
; 0.107  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.895      ; 3.957      ;
; 0.216  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.471      ;
; 0.217  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.472      ;
; 0.284  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.027      ; 1.536      ;
; 0.312  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.907      ; 4.654      ;
; 0.312  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.907      ; 4.654      ;
; 0.349  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 1.592      ;
; 0.378  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.633      ;
; 0.379  ; JTAG_NEXUS_TCK                                                                                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck1_Z                                                                          ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.901      ; 4.005      ;
; 0.390  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.645      ;
; 0.390  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.645      ;
; 0.394  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.649      ;
; 0.394  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 1.637      ;
; 0.415  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.684      ;
; 0.416  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.684      ;
; 0.420  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.028      ; 1.673      ;
; 0.439  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.694      ;
; 0.439  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.694      ;
; 0.442  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_8__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.697      ;
; 0.462  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.717      ;
; 0.464  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.719      ;
; 0.469  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.738      ;
; 0.480  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.735      ;
; 0.491  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.746      ;
; 0.491  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.746      ;
; 0.503  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.758      ;
; 0.511  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.766      ;
; 0.519  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.774      ;
; 0.527  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.782      ;
; 0.540  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_0__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.025      ; 1.790      ;
; 0.541  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.796      ;
; 0.542  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.029      ; 1.796      ;
; 0.544  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.799      ;
; 0.555  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.810      ;
; 0.566  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.019      ; 1.810      ;
; 0.592  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.847      ;
; 0.593  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.848      ;
; 0.595  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.907      ; 4.457      ;
; 0.595  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.907      ; 4.457      ;
; 0.597  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.852      ;
; 0.597  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.852      ;
; 0.599  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.027      ; 1.851      ;
; 0.600  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.855      ;
; 0.600  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.855      ;
; 0.600  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.855      ;
; 0.612  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.419      ; 1.261      ;
; 0.618  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 1.861      ;
; 0.618  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.015      ; 1.858      ;
; 0.620  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.889      ;
; 0.628  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_3__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.896      ;
; 0.653  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 1.896      ;
; 0.661  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.916      ;
; 0.663  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck2_Z                                                                                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck3_Z                                                                          ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.932      ;
; 0.669  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.443      ; 1.342      ;
; 0.687  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.956      ;
; 0.702  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.445      ; 1.377      ;
; 0.703  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|rst_Z                                                        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.029      ; 1.957      ;
; 0.709  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.964      ;
; 0.710  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 0.979      ;
; 0.711  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.445      ; 1.386      ;
; 0.722  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.977      ;
; 0.725  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 1.968      ;
; 0.730  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.985      ;
; 0.738  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 1.993      ;
; 0.740  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.443      ; 1.413      ;
; 0.758  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.013      ;
; 0.760  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.003      ;
; 0.764  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.007      ;
; 0.768  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_5__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.036      ;
; 0.775  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.018      ;
; 0.781  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.036      ;
; 0.787  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.029      ; 2.041      ;
; 0.794  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.423      ; 1.447      ;
; 0.795  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.050      ;
; 0.804  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z                                                                     ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.419      ; 1.453      ;
; 0.817  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.114      ;
; 0.819  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                                           ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff1_Z                                                                     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 1.088      ;
; 0.832  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_18__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.073      ;
; 0.832  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.087      ;
; 0.833  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.088      ;
; 0.845  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_9__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.113      ;
; 0.845  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.113      ;
; 0.845  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.113      ;
; 0.853  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.121      ;
; 0.859  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.127      ;
; 0.866  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.134      ;
; 0.868  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z                                                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.136      ;
; 0.873  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_1__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.074      ; 1.142      ;
; 0.876  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.021      ; 2.122      ;
; 0.877  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_3__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.145      ;
; 0.878  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_2__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_2__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.077      ; 1.150      ;
; 0.879  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.030      ; 2.134      ;
; 0.882  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.125      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; -0.492 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 2.465      ;
; 0.416  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.684      ;
; 0.417  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.607  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.713      ;
; 0.693  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.694  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.962      ;
; 0.694  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.962      ;
; 0.694  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.962      ;
; 0.694  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.695  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.963      ;
; 0.697  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.699  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.967      ;
; 0.699  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.966      ;
; 0.714  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.981      ;
; 0.716  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.984      ;
; 0.717  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.985      ;
; 0.721  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.988      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 0.979  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.442      ;
; 1.013  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.281      ;
; 1.013  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.281      ;
; 1.014  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.281      ;
; 1.015  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.016  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.284      ;
; 1.016  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.284      ;
; 1.016  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.017  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.284      ;
; 1.018  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.286      ;
; 1.018  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.286      ;
; 1.018  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.018  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.028  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.296      ;
; 1.028  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.296      ;
; 1.029  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.296      ;
; 1.031  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.299      ;
; 1.031  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.032  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.299      ;
; 1.059  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.742      ; 4.026      ;
; 1.077  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.762      ; 4.034      ;
; 1.112  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.380      ;
; 1.112  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.379      ;
; 1.115  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.383      ;
; 1.115  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.382      ;
; 1.135  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.403      ;
; 1.135  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.403      ;
; 1.136  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.403      ;
; 1.138  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.406      ;
; 1.138  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.405      ;
; 1.139  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.406      ;
; 1.140  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.408      ;
; 1.140  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.407      ;
; 1.150  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.418      ;
; 1.151  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.418      ;
; 1.153  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.421      ;
; 1.154  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.421      ;
; 1.237  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.505      ;
; 1.237  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.504      ;
; 1.257  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.525      ;
; 1.258  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.525      ;
; 1.260  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.528      ;
; 1.261  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.528      ;
; 1.289  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.268      ; 2.752      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.483  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 5.089      ;
; 1.503  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.044      ; 1.742      ;
; 1.603  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.871      ;
; 1.603  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.871      ;
; 1.603  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.871      ;
; 1.603  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.871      ;
; 1.603  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.871      ;
; 1.644  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.044      ; 1.883      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.993      ;
; 1.725  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.993      ;
; 1.728  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 2.742      ; 4.195      ;
; 1.857  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 2.125      ;
; 1.886  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 2.153      ;
; 1.886  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 2.153      ;
; 1.887  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 2.155      ;
; 1.887  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 2.155      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                               ; To Node                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.669      ;
; 0.414 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.684      ;
; 0.414 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.684      ;
; 0.465 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_4__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.735      ;
; 0.468 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_15__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_14__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.488 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.757      ;
; 0.488 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_0__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.758      ;
; 0.489 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_3__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.759      ;
; 0.490 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.760      ;
; 0.491 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_7__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.760      ;
; 0.537 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.807      ;
; 0.552 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.822      ;
; 0.560 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.830      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_6__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.873      ;
; 0.625 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.895      ;
; 0.625 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_7__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.895      ;
; 0.639 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.908      ;
; 0.642 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.912      ;
; 0.642 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.912      ;
; 0.642 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.911      ;
; 0.642 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.912      ;
; 0.642 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.912      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_24__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.912      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_16__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.913      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_9__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.913      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.913      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.913      ;
; 0.644 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_26__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.913      ;
; 0.644 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_20__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.914      ;
; 0.644 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_18__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.914      ;
; 0.644 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.914      ;
; 0.645 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.915      ;
; 0.647 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.916      ;
; 0.649 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.539      ; 1.383      ;
; 0.661 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.102      ; 0.958      ;
; 0.663 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.933      ;
; 0.663 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.933      ;
; 0.664 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.934      ;
; 0.664 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.933      ;
; 0.664 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.934      ;
; 0.664 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.933      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.934      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.934      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.102      ; 0.962      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.934      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.934      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.665 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.936      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.935      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.936      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.936      ;
; 0.666 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.936      ;
; 0.667 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.936      ;
; 0.667 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.936      ;
; 0.667 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.937      ;
; 0.668 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.937      ;
; 0.675 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.951      ;
; 0.680 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.956      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.956      ;
; 0.687 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.957      ;
; 0.691 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.540      ; 1.426      ;
; 0.695 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.971      ;
; 0.706 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.982      ;
; 0.707 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.983      ;
; 0.712 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.988      ;
; 0.719 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 0.995      ;
; 0.725 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.001      ;
; 0.764 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 1.033      ;
; 0.764 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 1.033      ;
; 0.765 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 1.034      ;
; 0.776 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.046      ;
; 0.778 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.048      ;
; 0.792 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_29__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_28__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 1.063      ;
; 0.793 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_2__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_1__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 1.064      ;
; 0.822 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.102      ; 1.119      ;
; 0.823 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_7__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_6__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 1.094      ;
; 0.830 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_13__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_12__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 1.101      ;
; 0.832 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.102      ;
; 0.834 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.102      ; 1.131      ;
; 0.835 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_23__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.105      ;
; 0.836 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_30__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_29__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.106      ;
; 0.836 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_5__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 1.105      ;
; 0.836 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.106      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SW_USER2'                                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.445 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.044      ; 0.684      ;
; 0.835 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.080      ;
; 1.072 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.317      ;
; 1.075 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.320      ;
; 1.076 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.321      ;
; 1.081 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.326      ;
; 1.082 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.327      ;
; 1.098 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.343      ;
; 1.099 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.344      ;
; 1.101 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.346      ;
; 1.202 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.447      ;
; 1.207 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.452      ;
; 1.237 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.482      ;
; 1.238 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.483      ;
; 1.289 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.534      ;
; 1.290 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.535      ;
; 1.291 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.536      ;
; 1.343 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.588      ;
; 1.374 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.619      ;
; 1.379 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.624      ;
; 1.384 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.629      ;
; 1.389 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.634      ;
; 1.390 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.635      ;
; 1.396 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.641      ;
; 1.409 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.654      ;
; 1.414 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.659      ;
; 1.423 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.668      ;
; 1.429 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.674      ;
; 1.430 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.675      ;
; 1.431 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.676      ;
; 1.466 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.711      ;
; 1.474 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.719      ;
; 1.476 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.721      ;
; 1.481 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.726      ;
; 1.482 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.727      ;
; 1.486 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.731      ;
; 1.489 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.734      ;
; 1.490 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.735      ;
; 1.500 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.745      ;
; 1.503 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.748      ;
; 1.522 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.767      ;
; 1.522 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.767      ;
; 1.523 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.768      ;
; 1.530 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.775      ;
; 1.576 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.821      ;
; 1.592 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.837      ;
; 1.592 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.837      ;
; 1.670 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.915      ;
; 1.671 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.916      ;
; 1.746 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.991      ;
; 1.747 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.992      ;
; 1.748 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 1.993      ;
; 1.762 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 2.007      ;
; 1.763 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 2.008      ;
; 1.979 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 2.224      ;
; 1.987 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 2.232      ;
; 1.988 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.050      ; 2.233      ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.703 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.973      ;
; 0.704 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.974      ;
; 0.709 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.979      ;
; 0.710 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.980      ;
; 0.710 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.980      ;
; 0.711 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 0.981      ;
; 0.712 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.981      ;
; 0.715 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.984      ;
; 0.726 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.995      ;
; 0.727 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.996      ;
; 0.729 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.998      ;
; 0.730 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 0.999      ;
; 0.877 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.147      ;
; 0.883 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.153      ;
; 0.884 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.153      ;
; 0.885 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.154      ;
; 0.886 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.156      ;
; 0.896 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.166      ;
; 0.896 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.166      ;
; 0.899 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.169      ;
; 0.899 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.169      ;
; 0.900 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.170      ;
; 0.903 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.172      ;
; 0.904 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.173      ;
; 0.906 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.175      ;
; 0.907 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.176      ;
; 1.025 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.295      ;
; 1.026 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.296      ;
; 1.026 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.296      ;
; 1.027 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.297      ;
; 1.027 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.297      ;
; 1.034 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.303      ;
; 1.034 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.303      ;
; 1.043 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.313      ;
; 1.044 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.314      ;
; 1.044 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.314      ;
; 1.048 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.317      ;
; 1.049 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.318      ;
; 1.058 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.327      ;
; 1.063 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.332      ;
; 1.086 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.093      ; 1.374      ;
; 1.087 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.093      ; 1.375      ;
; 1.117 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.387      ;
; 1.119 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.389      ;
; 1.130 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.399      ;
; 1.147 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.417      ;
; 1.148 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.418      ;
; 1.149 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.419      ;
; 1.149 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.419      ;
; 1.156 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.425      ;
; 1.156 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.425      ;
; 1.161 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.431      ;
; 1.166 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.436      ;
; 1.166 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.436      ;
; 1.170 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.439      ;
; 1.171 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.440      ;
; 1.173 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.443      ;
; 1.173 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.443      ;
; 1.180 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.449      ;
; 1.184 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.453      ;
; 1.185 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.454      ;
; 1.204 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.073      ; 1.472      ;
; 1.207 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.091      ; 1.493      ;
; 1.210 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.479      ;
; 1.216 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.486      ;
; 1.220 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.490      ;
; 1.228 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.498      ;
; 1.237 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.507      ;
; 1.237 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.506      ;
; 1.237 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.073      ; 1.505      ;
; 1.238 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.508      ;
; 1.239 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.509      ;
; 1.239 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.509      ;
; 1.239 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.509      ;
; 1.239 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.509      ;
; 1.239 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.508      ;
; 1.239 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.508      ;
; 1.240 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.509      ;
; 1.241 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.511      ;
; 1.244 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.514      ;
; 1.244 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.514      ;
; 1.247 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.073      ; 1.515      ;
; 1.249 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.518      ;
; 1.251 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.073      ; 1.519      ;
; 1.252 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.521      ;
; 1.253 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.523      ;
; 1.254 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.524      ;
; 1.256 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.525      ;
; 1.258 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.527      ;
; 1.259 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.528      ;
; 1.260 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.529      ;
; 1.269 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.539      ;
; 1.270 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.540      ;
; 1.271 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.541      ;
; 1.278 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.547      ;
; 1.278 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.547      ;
; 1.283 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.553      ;
; 1.288 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.075      ; 1.558      ;
; 1.292 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.561      ;
; 1.293 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.074      ; 1.562      ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.383      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.390 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.298      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.318 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.216      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.223 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.131      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.166 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 3.064      ;
; -2.130 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.038      ;
; -2.130 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 3.038      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -2.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.979      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.993 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 2.891      ;
; -1.963 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.871      ;
; -1.963 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.871      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.898 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.806      ;
; -1.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.719      ;
; -1.811 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.719      ;
; -1.638 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.546      ;
; -1.638 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 2.546      ;
; -1.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.084     ; 1.649      ;
; -1.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.084     ; 1.649      ;
; -1.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.084     ; 1.649      ;
; -1.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.084     ; 1.649      ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                         ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -2.260 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.116      ; 3.868      ;
; -1.910 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.116      ; 4.018      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.801 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.704      ; 5.497      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.754 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.704      ; 4.950      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.659 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 3.706      ; 4.857      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; -0.284 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 3.706      ; 4.982      ;
; 0.407  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 2.613      ; 2.698      ;
; 0.710  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 2.613      ; 2.895      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.574 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.313      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 3.146      ;
; -1.305 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 3.038      ;
; -1.302 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 3.036      ;
; -1.293 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 3.026      ;
; -1.293 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 3.026      ;
; -1.272 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 3.006      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.994      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.988      ;
; -1.254 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.988      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.246 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.986      ;
; -1.138 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.871      ;
; -1.135 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.869      ;
; -1.126 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.859      ;
; -1.126 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.859      ;
; -1.105 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.839      ;
; -1.087 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.821      ;
; -1.087 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.082 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.747      ; 2.821      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -1.079 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.819      ;
; -0.986 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.719      ;
; -0.983 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.717      ;
; -0.974 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.707      ;
; -0.974 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.707      ;
; -0.953 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.687      ;
; -0.935 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.669      ;
; -0.935 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.669      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.927 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.667      ;
; -0.813 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.546      ;
; -0.810 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.544      ;
; -0.801 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.534      ;
; -0.801 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.741      ; 2.534      ;
; -0.780 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.514      ;
; -0.762 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.496      ;
; -0.762 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.742      ; 2.496      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.754 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.748      ; 2.494      ;
; -0.625 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.367      ;
; -0.625 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.367      ;
; -0.458 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.200      ;
; -0.458 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.200      ;
; -0.306 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.048      ;
; -0.306 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 2.048      ;
; -0.133 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 1.875      ;
; -0.133 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.750      ; 1.875      ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                          ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.163 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 2.742      ; 2.804      ;
; 0.147  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 2.742      ; 2.614      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 0.701  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.881      ; 4.807      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.078  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.881      ; 4.684      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.174  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 3.878      ; 4.777      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 1.199  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 3.878      ; 5.302      ;
; 2.474  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.183      ; 3.882      ;
; 2.831  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.183      ; 3.739      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; 0.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 1.745      ;
; 0.494 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 1.745      ;
; 0.592 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 1.843      ;
; 0.592 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 1.843      ;
; 0.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 2.024      ;
; 0.773 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 2.024      ;
; 0.939 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 2.190      ;
; 0.939 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.026      ; 2.190      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.960 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.208      ;
; 0.969 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.212      ;
; 0.973 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.215      ;
; 0.973 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.215      ;
; 1.027 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.270      ;
; 1.033 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.274      ;
; 1.033 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.274      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.300      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.058 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.306      ;
; 1.067 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.310      ;
; 1.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.313      ;
; 1.071 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.313      ;
; 1.125 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.368      ;
; 1.131 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.372      ;
; 1.131 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.372      ;
; 1.156 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.398      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.454      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.487      ;
; 1.248 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.491      ;
; 1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.494      ;
; 1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.494      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.552      ;
; 1.306 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.549      ;
; 1.312 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.553      ;
; 1.312 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.553      ;
; 1.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.579      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.405 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.653      ;
; 1.414 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.657      ;
; 1.418 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.660      ;
; 1.418 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.660      ;
; 1.472 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.018      ; 2.715      ;
; 1.478 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.719      ;
; 1.478 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.016      ; 2.719      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.733      ;
; 1.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.017      ; 2.745      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
; 1.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.023      ; 2.899      ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.701 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.480      ;
; 1.701 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.480      ;
; 1.701 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.480      ;
; 1.701 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.480      ;
; 2.015 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.300      ;
; 2.015 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.300      ;
; 2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.398      ;
; 2.113 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.398      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.491      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.263 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.537      ;
; 2.294 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.579      ;
; 2.294 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.579      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.304 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.589      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.361 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.635      ;
; 2.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.745      ;
; 2.460 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.745      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.485 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.770      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.542 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.816      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.651 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.090      ; 2.936      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
; 2.708 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.982      ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                           ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                                                                            ; Clock Edge ; Target                                                                                                           ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_we_reg       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_0__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_1__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_2__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_3__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_4__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_5__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_6__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_7__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_10__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_2__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_8__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z                                                         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_0__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_10__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_11__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_12__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_13__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_14__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_15__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_16__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_17__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_18__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_19__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_20__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_7__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_8__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_9__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z                                   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_0__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_3__Z                                        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_0__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_2__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_4__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_6__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_0__Z                                              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_15__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                                                                                        ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                                                                                        ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                                                                                ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z              ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_0__Z ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_19__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_20__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_6__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_10__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_12__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_13__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_17__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_18__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_19__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_20__Z         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_3__Z          ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                 ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK_BRD ; Rise       ; CLK_BRD                                                                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; 0.228  ; 0.444        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; 0.267  ; 0.483        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.269  ; 0.485        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; 0.328  ; 0.512        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; 0.329  ; 0.513        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; 0.330  ; 0.514        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; 0.367  ; 0.551        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; 0.378  ; 0.562        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~input|o                                                                  ;
; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|inclk[0]                                                    ;
; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|outclk                                                      ;
; 0.461  ; 0.461        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|clk                                                 ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_10|ff1|dffs[0]|clk                                                      ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_11|ff1|dffs[0]|clk                                                      ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER3'                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER3 ; Rise       ; SW_USER3                                                                                           ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -0.125 ; 0.091        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.145  ; 0.145        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
; 0.148  ; 0.148        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.148  ; 0.148        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.404  ; 0.404        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
; 0.412  ; 0.412        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.590  ; 0.590        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; 0.705  ; 0.889        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; 0.835  ; 0.835        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.835  ; 0.835        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.838  ; 0.838        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER2'                                                                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER2 ; Rise       ; SW_USER2                                                                                             ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.154  ; 0.370        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.424  ; 0.424        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.438  ; 0.622        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.571  ; 0.571        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SW_USER4'                                                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                              ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER4 ; Rise       ; SW_USER4                                                                            ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.145  ; 0.361        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.340  ; 0.340        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.415  ; 0.415        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.417  ; 0.417        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.417  ; 0.417        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 0.450  ; 0.634        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.451  ; 0.635        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.462  ; 0.462        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.538  ; 0.538        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.581  ; 0.581        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.581  ; 0.581        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 0.583  ; 0.583        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.584  ; 0.584        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.645  ; 0.645        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
; 0.653  ; 0.653        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.064  ; 0.280        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.065  ; 0.281        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.086  ; 0.302        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.212  ; 0.428        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.335  ; 0.335        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.337  ; 0.337        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.337  ; 0.337        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.356  ; 0.356        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.384  ; 0.568        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.482  ; 0.482        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.506  ; 0.690        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.517  ; 0.517        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.525  ; 0.709        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.526  ; 0.710        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.639  ; 0.639        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.656  ; 0.656        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.656  ; 0.656        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.659  ; 0.659        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.074  ; 0.510  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.898  ; 1.658  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 1.390  ; 1.566  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.173  ; 3.039  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; 3.379  ; 3.350  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; 3.239  ; 3.289  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; 2.022  ; 2.173  ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 0.500  ; 0.935  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; -0.985 ; -1.092 ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; -0.582 ; -0.435 ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.498  ; 0.823  ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; -0.383 ; -0.212 ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; -1.051 ; -0.851 ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; -0.312 ; 0.008  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.500  ; 0.856  ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.436  ; 0.935  ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; -0.809 ; -0.417 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                          ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.487  ; 0.091  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.914 ; -1.050 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.637 ; -1.013 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -2.358 ; -2.495 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; -2.032 ; -2.120 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; -2.667 ; -2.761 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; -1.492 ; -1.615 ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 1.735  ; 1.833  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; 1.735  ; 1.833  ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; 1.251  ; 1.109  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.216  ; -0.100 ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; 1.062  ; 0.894  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; 1.701  ; 1.508  ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; 0.992  ; 0.683  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.215  ; -0.131 ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.277  ; -0.206 ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; 1.554  ; 1.229  ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                               ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.857 ; 10.288 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.857 ; 10.288 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.940  ; 6.667  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.940  ; 6.667  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.226  ; 8.791  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.226  ; 8.791  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.579  ; 7.150  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 17.459 ; 16.557 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 8.638  ; 8.067  ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 8.638  ; 8.067  ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 13.438 ; 12.833 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 12.405 ; 12.018 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 13.438 ; 12.833 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 11.255 ; 11.067 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 12.324 ; 12.073 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 16.619 ; 15.771 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 15.560 ; 14.648 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 14.987 ; 14.245 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 15.874 ; 15.468 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 16.619 ; 15.771 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 13.620 ; 12.979 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 14.375 ; 13.620 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 11.421 ; 11.252 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 12.223 ; 12.015 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 17.863 ; 16.793 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 16.600 ; 15.803 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 15.473 ; 14.673 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 17.392 ; 16.418 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 17.513 ; 16.305 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 16.264 ; 15.385 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 17.863 ; 16.793 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 17.635 ; 16.627 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 13.161 ; 12.704 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 8.534  ; 8.456  ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.534  ; 8.456  ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.117  ; 7.956  ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.287  ; 8.891  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.287  ; 8.891  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.756  ; 8.439  ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 8.534  ; 8.456  ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.534  ; 8.456  ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.117  ; 7.956  ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.287  ; 8.891  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.287  ; 8.891  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.756  ; 8.439  ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 16.179 ; 15.301 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 13.749 ; 13.405 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 15.744 ; 14.971 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 15.033 ; 14.346 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 16.179 ; 15.301 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 13.592 ; 13.093 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 15.229 ; 14.529 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 15.001 ; 14.364 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 13.995 ; 13.381 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 12.720 ; 12.178 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 12.720 ; 12.178 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 12.475 ; 11.898 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 11.336 ; 11.045 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 11.358 ; 11.048 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                       ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.511 ; 9.962  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 10.511 ; 9.962  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.759  ; 6.497  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 6.759  ; 6.497  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.373  ; 6.960  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8.955  ; 8.537  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.373  ; 6.960  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 9.524  ; 9.176  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 8.433  ; 7.885  ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 8.433  ; 7.885  ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 8.433  ; 7.885  ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 12.031 ; 11.655 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 13.020 ; 12.437 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 8.433  ; 7.885  ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 11.935 ; 11.690 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 11.091 ; 10.928 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 15.067 ; 14.190 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 14.481 ; 13.750 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 15.384 ; 14.982 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 16.044 ; 15.214 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 13.160 ; 12.525 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 13.882 ; 13.140 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 11.091 ; 10.928 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 11.861 ; 11.661 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 12.761 ; 12.320 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 16.065 ; 15.297 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 14.983 ; 14.213 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 16.826 ; 15.888 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 16.942 ; 15.779 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 15.735 ; 14.886 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 17.269 ; 16.239 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 17.053 ; 16.084 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 12.761 ; 12.320 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 7.935  ; 7.778  ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.334  ; 8.256  ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 7.935  ; 7.778  ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 8.549  ; 8.241  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.048  ; 8.666  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.549  ; 8.241  ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 7.935  ; 7.778  ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 8.334  ; 8.256  ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 7.935  ; 7.778  ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 8.549  ; 8.241  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.048  ; 8.666  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 8.549  ; 8.241  ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 13.174 ; 12.690 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 13.331 ; 12.997 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 15.220 ; 14.476 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 14.565 ; 13.904 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 15.666 ; 14.821 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 13.174 ; 12.690 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 14.744 ; 14.069 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 14.529 ; 13.915 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 13.505 ; 12.911 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 11.008 ; 10.726 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 12.335 ; 11.812 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 12.101 ; 11.544 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 11.008 ; 10.726 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 11.029 ; 10.729 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF     ; FR     ; FF ;
+------------+-------------+----+--------+--------+----+
; HA[12]     ; LED_G[0]    ;    ; 10.874 ; 11.464 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 9.941  ; 10.388 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 11.183 ; 11.251 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 11.235 ; 11.835 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 8.648  ; 8.987  ;    ;
; HA[17]     ; LED_G[5]    ;    ; 9.489  ; 10.014 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 7.985  ; 8.116  ;    ;
; HA[19]     ; LED_G[7]    ;    ; 7.549  ; 7.821  ;    ;
+------------+-------------+----+--------+--------+----+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF     ; FR     ; FF ;
+------------+-------------+----+--------+--------+----+
; HA[12]     ; LED_G[0]    ;    ; 10.579 ; 11.146 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 9.681  ; 10.110 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 10.935 ; 10.996 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 10.925 ; 11.501 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 8.431  ; 8.758  ;    ;
; HA[17]     ; LED_G[5]    ;    ; 9.239  ; 9.743  ;    ;
; HA[18]     ; LED_G[6]    ;    ; 7.803  ; 7.930  ;    ;
; HA[19]     ; LED_G[7]    ;    ; 7.386  ; 7.647  ;    ;
+------------+-------------+----+--------+--------+----+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                        ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -3.522 ; -190.530      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.698 ; -15.596       ;
; JTAG_NEXUS_TCK                                                                   ; -1.366 ; -247.118      ;
; CLK_BRD                                                                          ; -1.317 ; -28.916       ;
; SW_USER3                                                                         ; -0.285 ; -1.216        ;
; SW_USER4                                                                         ; -0.272 ; -1.198        ;
; SW_USER2                                                                         ; -0.219 ; -1.146        ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                         ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; SW_USER3                                                                         ; -1.068 ; -1.068        ;
; SW_USER4                                                                         ; -0.734 ; -5.746        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.379 ; -2.274        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.297 ; -0.931        ;
; JTAG_NEXUS_TCK                                                                   ; 0.185  ; 0.000         ;
; SW_USER2                                                                         ; 0.208  ; 0.000         ;
; CLK_BRD                                                                          ; 0.303  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                     ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.392 ; -11.067       ;
; JTAG_NEXUS_TCK                                                                   ; -0.727 ; -16.553       ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.314 ; -4.305        ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                      ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.133 ; -0.133        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.267  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                   ; 0.941  ; 0.000         ;
+----------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                          ;
+----------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                            ; Slack  ; End Point TNS ;
+----------------------------------------------------------------------------------+--------+---------------+
; JTAG_NEXUS_TCK                                                                   ; -3.000 ; -267.084      ;
; CLK_BRD                                                                          ; -3.000 ; -35.747       ;
; SW_USER3                                                                         ; -3.000 ; -12.873       ;
; SW_USER4                                                                         ; -3.000 ; -12.041       ;
; SW_USER2                                                                         ; -3.000 ; -11.640       ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -1.000 ; -151.000      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.000 ; -16.000       ;
+----------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                            ; To Node                                                                   ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -3.522 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.466      ;
; -3.522 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.466      ;
; -3.472 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.416      ;
; -3.472 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.416      ;
; -3.396 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.340      ;
; -3.396 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.340      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.281      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.231      ;
; -3.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.229      ;
; -3.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.229      ;
; -3.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.229      ;
; -3.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.229      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.322      ;
; -3.247 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.501      ;
; -3.247 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.501      ;
; -3.238 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.182      ;
; -3.238 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.182      ;
; -3.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.486      ;
; -3.231 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.486      ;
; -3.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.179      ;
; -3.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.179      ;
; -3.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.179      ;
; -3.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.179      ;
; -3.227 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.283      ;
; -3.227 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.079      ; 4.283      ;
; -3.214 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.468      ;
; -3.214 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.468      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.155      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.163 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.417      ;
; -3.153 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.103      ;
; -3.153 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.103      ;
; -3.153 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.103      ;
; -3.153 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.103      ;
; -3.149 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.074      ; 4.200      ;
; -3.149 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.074      ; 4.200      ;
; -3.149 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.074      ; 4.200      ;
; -3.149 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_7__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.074      ; 4.200      ;
; -3.142 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.397      ;
; -3.142 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.397      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.129 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 4.383      ;
; -3.097 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.352      ;
; -3.097 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.352      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.086 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 4.030      ;
; -3.073 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_3__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.328      ;
; -3.073 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_3__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.278      ; 4.328      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
; -3.053 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.043     ; 3.997      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -1.698 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.301      ;
; -1.656 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.259      ;
; -1.649 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.252      ;
; -1.628 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.231      ;
; -1.583 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.186      ;
; -1.559 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.162      ;
; -1.542 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -1.384     ; 1.145      ;
; -1.487 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 0.488      ; 2.452      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.307 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 3.570      ;
; -1.074 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.360      ;
; -1.025 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.311      ;
; -1.025 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.311      ;
; -1.004 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.290      ;
; -0.957 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.243      ;
; -0.937 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.223      ;
; -0.890 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.701     ; 1.176      ;
; -0.773 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.168      ; 2.418      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.525 ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.786      ;
; -0.478 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.488      ; 1.943      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.455 ; SW_USER4                                                                                  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 3.218      ;
; -0.274 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.022     ; 1.239      ;
; -0.218 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.022     ; 1.183      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.192 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.141      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.136 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.085      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.117 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.067      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.096 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 1.045      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.059 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 1.009      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.049 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.998      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.043 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 0.992      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
; -0.024 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 0.974      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                               ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                     ; To Node                                                                                                                                ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -1.366 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.298      ;
; -1.366 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.298      ;
; -1.366 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.298      ;
; -1.366 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.298      ;
; -1.366 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.298      ;
; -1.299 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.232      ;
; -1.299 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.232      ;
; -1.299 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.232      ;
; -1.271 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.204      ;
; -1.271 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.204      ;
; -1.271 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.204      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_10__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.261 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.194      ;
; -1.256 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.206      ;
; -1.256 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.206      ;
; -1.256 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.206      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_20__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_19__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.252 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_12__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.185      ;
; -1.235 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.176      ;
; -1.235 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.176      ;
; -1.235 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.176      ;
; -1.235 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.176      ;
; -1.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.175      ;
; -1.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.175      ;
; -1.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.175      ;
; -1.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.175      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 2.167      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 2.167      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 2.167      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 2.167      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.164      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.164      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.164      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.164      ;
; -1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.164      ;
; -1.227 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.039     ; 2.175      ;
; -1.227 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_6__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.039     ; 2.175      ;
; -1.207 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.140      ;
; -1.207 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.140      ;
; -1.207 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.140      ;
; -1.202 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.051     ; 2.138      ;
; -1.200 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.133      ;
; -1.200 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.133      ;
; -1.200 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.133      ;
; -1.198 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 2.140      ;
; -1.197 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 2.139      ;
; -1.197 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.129      ;
; -1.197 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.129      ;
; -1.197 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.129      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.195 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.128      ;
; -1.192 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.124      ;
; -1.192 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.124      ;
; -1.192 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.124      ;
; -1.191 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 2.126      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_0__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.188 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.121      ;
; -1.182 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.123      ;
; -1.182 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.123      ;
; -1.182 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.123      ;
; -1.182 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 2.123      ;
; -1.181 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.114      ;
; -1.181 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.114      ;
; -1.181 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 2.114      ;
; -1.175 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.125      ;
; -1.175 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.125      ;
; -1.175 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.125      ;
; -1.174 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.124      ;
; -1.174 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.124      ;
; -1.174 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 2.124      ;
; -1.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.055     ; 2.104      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.317 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.266      ;
; -1.313 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.262      ;
; -1.268 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.217      ;
; -1.264 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.213      ;
; -1.249 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.198      ;
; -1.245 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.194      ;
; -1.221 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.170      ;
; -1.218 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.167      ;
; -1.217 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.166      ;
; -1.200 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.149      ;
; -1.200 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.149      ;
; -1.196 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.145      ;
; -1.194 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.143      ;
; -1.187 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.136      ;
; -1.185 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.134      ;
; -1.181 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.130      ;
; -1.179 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.128      ;
; -1.177 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.126      ;
; -1.166 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.116      ;
; -1.153 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.102      ;
; -1.152 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.102      ;
; -1.150 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.099      ;
; -1.149 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.098      ;
; -1.149 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.098      ;
; -1.148 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.097      ;
; -1.145 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.094      ;
; -1.144 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.093      ;
; -1.144 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.094      ;
; -1.132 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.081      ;
; -1.132 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.081      ;
; -1.132 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.082      ;
; -1.128 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.077      ;
; -1.126 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.075      ;
; -1.126 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.076      ;
; -1.125 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.075      ;
; -1.120 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.069      ;
; -1.119 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.068      ;
; -1.117 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.066      ;
; -1.116 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.065      ;
; -1.113 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.062      ;
; -1.111 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.060      ;
; -1.109 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.058      ;
; -1.099 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.048      ;
; -1.098 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.048      ;
; -1.095 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.044      ;
; -1.085 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.034      ;
; -1.084 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.034      ;
; -1.082 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.031      ;
; -1.081 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.030      ;
; -1.081 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.030      ;
; -1.080 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.029      ;
; -1.077 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.026      ;
; -1.076 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.025      ;
; -1.076 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.026      ;
; -1.064 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.013      ;
; -1.064 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.013      ;
; -1.064 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.014      ;
; -1.063 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.012      ;
; -1.060 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.009      ;
; -1.059 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.008      ;
; -1.058 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.007      ;
; -1.058 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.008      ;
; -1.057 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 2.007      ;
; -1.052 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.001      ;
; -1.051 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 2.000      ;
; -1.049 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.998      ;
; -1.048 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.997      ;
; -1.045 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.994      ;
; -1.043 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.992      ;
; -1.043 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.992      ;
; -1.041 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.990      ;
; -1.031 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.980      ;
; -1.031 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.980      ;
; -1.030 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.980      ;
; -1.027 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.976      ;
; -1.017 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.966      ;
; -1.016 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.966      ;
; -1.014 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.963      ;
; -1.013 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.962      ;
; -1.013 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.962      ;
; -1.012 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.961      ;
; -1.011 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.961      ;
; -1.009 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.958      ;
; -1.009 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.959      ;
; -1.008 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.957      ;
; -1.008 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.958      ;
; -0.996 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.945      ;
; -0.996 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.945      ;
; -0.996 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.946      ;
; -0.995 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.944      ;
; -0.992 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.941      ;
; -0.991 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.940      ;
; -0.990 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.939      ;
; -0.990 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.940      ;
; -0.989 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.939      ;
; -0.986 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.936      ;
; -0.984 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.933      ;
; -0.983 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.932      ;
; -0.981 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.038     ; 1.930      ;
; -0.981 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.037     ; 1.931      ;
+--------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SW_USER3'                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.285 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.235      ;
; -0.219 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.169      ;
; -0.180 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 1.129      ;
; -0.179 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.129      ;
; -0.151 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.101      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.133 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.083      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.131 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.081      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.127 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.077      ;
; -0.112 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.062      ;
; -0.069 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 1.018      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.063 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.013      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.056 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 1.006      ;
; -0.034 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.983      ;
; -0.002 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.951      ;
; -0.002 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.951      ;
; -0.002 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.951      ;
; -0.002 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.951      ;
; -0.002 ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.951      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.005  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.945      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.009  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.941      ;
; 0.067  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.037     ; 0.883      ;
; 0.590  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 1.000        ; -0.038     ; 0.359      ;
; 1.360  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.713      ;
; 1.383  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.690      ;
; 1.433  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.640      ;
; 1.434  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.639      ;
; 1.439  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.634      ;
; 1.447  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.626      ;
; 1.449  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.624      ;
; 1.486  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; 0.500        ; 2.596      ; 1.587      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SW_USER4'                                                                                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.272 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.223      ;
; -0.247 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.198      ;
; -0.238 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.189      ;
; -0.238 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.188      ;
; -0.213 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.163      ;
; -0.204 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.154      ;
; -0.202 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.153      ;
; -0.187 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.137      ;
; -0.162 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.112      ;
; -0.153 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.103      ;
; -0.142 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.092      ;
; -0.139 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.089      ;
; -0.134 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.085      ;
; -0.133 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.083      ;
; -0.120 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.070      ;
; -0.108 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.058      ;
; -0.099 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.049      ;
; -0.071 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.021      ;
; -0.069 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 1.020      ;
; -0.068 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.018      ;
; -0.067 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.017      ;
; -0.067 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.017      ;
; -0.052 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 1.002      ;
; -0.036 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.036     ; 0.987      ;
; -0.018 ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.968      ;
; 0.000  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.950      ;
; 0.000  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.950      ;
; 0.001  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.949      ;
; 0.002  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.948      ;
; 0.002  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.948      ;
; 0.013  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.937      ;
; 0.014  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.936      ;
; 0.034  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.916      ;
; 0.042  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.908      ;
; 0.043  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.907      ;
; 0.043  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.907      ;
; 0.044  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.906      ;
; 0.044  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.906      ;
; 0.050  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.900      ;
; 0.070  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.880      ;
; 0.072  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.878      ;
; 0.110  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.840      ;
; 0.114  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.836      ;
; 0.115  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.835      ;
; 0.115  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.835      ;
; 0.115  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.835      ;
; 0.116  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.834      ;
; 0.128  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.822      ;
; 0.130  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.820      ;
; 0.172  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.778      ;
; 0.173  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.777      ;
; 0.173  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.777      ;
; 0.173  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.777      ;
; 0.222  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.728      ;
; 0.236  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.714      ;
; 0.323  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.627      ;
; 0.378  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 1.000        ; -0.037     ; 0.572      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.897  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.569      ; 2.149      ;
; 0.927  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; 0.500        ; 2.568      ; 2.118      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.108  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.796      ; 3.155      ;
; 1.138  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.500        ; 3.795      ; 3.124      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.277  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.796      ; 3.486      ;
; 1.296  ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 1.000        ; 3.795      ; 3.466      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SW_USER2'                                                                                                                                                                                                                                                     ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.219 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.202      ;
; -0.215 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.198      ;
; -0.181 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.164      ;
; -0.181 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.164      ;
; -0.180 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.163      ;
; -0.172 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.155      ;
; -0.171 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.154      ;
; -0.163 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.146      ;
; -0.159 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.142      ;
; -0.121 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.104      ;
; -0.119 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.102      ;
; -0.115 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.098      ;
; -0.115 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.098      ;
; -0.100 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.083      ;
; -0.096 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.079      ;
; -0.094 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.077      ;
; -0.084 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.067      ;
; -0.079 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.062      ;
; -0.061 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.044      ;
; -0.060 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.043      ;
; -0.052 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.035      ;
; -0.051 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.034      ;
; -0.051 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.034      ;
; -0.050 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.033      ;
; -0.049 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.032      ;
; -0.049 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.032      ;
; -0.046 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.029      ;
; -0.031 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.014      ;
; -0.028 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.011      ;
; -0.026 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.009      ;
; -0.024 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.007      ;
; -0.023 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.006      ;
; -0.018 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 1.001      ;
; -0.014 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.997      ;
; -0.002 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.985      ;
; 0.004  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.979      ;
; 0.005  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.978      ;
; 0.013  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.970      ;
; 0.021  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.962      ;
; 0.044  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.939      ;
; 0.045  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.938      ;
; 0.052  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.931      ;
; 0.062  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.921      ;
; 0.063  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.920      ;
; 0.069  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.914      ;
; 0.071  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.912      ;
; 0.071  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.912      ;
; 0.099  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.884      ;
; 0.121  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.862      ;
; 0.123  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.860      ;
; 0.124  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.859      ;
; 0.134  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.849      ;
; 0.136  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.847      ;
; 0.136  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.847      ;
; 0.192  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.791      ;
; 0.194  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.024     ; 0.789      ;
; 0.626  ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 1.000        ; -0.022     ; 0.359      ;
+--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SW_USER3'                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                            ; To Node                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.068 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.312      ;
; -1.067 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.313      ;
; -1.059 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.321      ;
; -1.026 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.354      ;
; -1.025 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.355      ;
; -1.022 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.358      ;
; -1.007 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.373      ;
; -0.986 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER3    ; -0.500       ; 2.766      ; 1.394      ;
; 0.192  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.314      ;
; 0.305  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.426      ;
; 0.309  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.430      ;
; 0.310  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.431      ;
; 0.310  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.431      ;
; 0.310  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.431      ;
; 0.310  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.431      ;
; 0.316  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.437      ;
; 0.397  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.518      ;
; 0.454  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.575      ;
; 0.459  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.580      ;
; 0.459  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.580      ;
; 0.468  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.589      ;
; 0.468  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.589      ;
; 0.469  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.590      ;
; 0.471  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.592      ;
; 0.471  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.592      ;
; 0.472  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.593      ;
; 0.522  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.643      ;
; 0.522  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.643      ;
; 0.525  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.646      ;
; 0.525  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.646      ;
; 0.534  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.655      ;
; 0.535  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.656      ;
; 0.537  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.658      ;
; 0.538  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.659      ;
; 0.549  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.670      ;
; 0.552  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.673      ;
; 0.588  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.709      ;
; 0.591  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.712      ;
; 0.601  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.722      ;
; 0.604  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.725      ;
; 0.615  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.736      ;
; 0.618  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.739      ;
; 0.620  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.742      ;
; 0.681  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.802      ;
; 0.684  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.805      ;
; 0.706  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.828      ;
; 0.732  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.853      ;
; 0.732  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.853      ;
; 0.735  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.856      ;
; 0.735  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.856      ;
; 0.735  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.856      ;
; 0.735  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.856      ;
; 0.754  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.876      ;
; 0.756  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.878      ;
; 0.778  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.899      ;
; 0.778  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.899      ;
; 0.778  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.899      ;
; 0.820  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.942      ;
; 0.820  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.942      ;
; 0.822  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 0.944      ;
; 0.833  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.954      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.835  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.956      ;
; 0.844  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.965      ;
; 0.844  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.965      ;
; 0.844  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.965      ;
; 0.844  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.965      ;
; 0.844  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.037      ; 0.965      ;
; 0.887  ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]        ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ; SW_USER3     ; SW_USER3    ; 0.000        ; 0.038      ; 1.009      ;
+--------+------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SW_USER4'                                                                                                                                                                                                                                                                                           ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                             ; Launch Clock                                                                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.734 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.933      ; 3.323      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.716 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; 0.000        ; 3.934      ; 3.342      ;
; -0.563 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.765      ; 1.816      ;
; -0.548 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.933      ; 3.009      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.545 ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; SW_USER4    ; -0.500       ; 2.766      ; 1.835      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; -0.519 ; SW_USER3                                                                                  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; SW_USER4    ; -0.500       ; 3.934      ; 3.039      ;
; 0.413  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.534      ;
; 0.414  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.535      ;
; 0.462  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.583      ;
; 0.462  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.583      ;
; 0.463  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.584      ;
; 0.463  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.584      ;
; 0.467  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.588      ;
; 0.524  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.645      ;
; 0.525  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.646      ;
; 0.525  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.646      ;
; 0.526  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.647      ;
; 0.531  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.652      ;
; 0.536  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.657      ;
; 0.537  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.658      ;
; 0.547  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.669      ;
; 0.548  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.669      ;
; 0.548  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.670      ;
; 0.549  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.670      ;
; 0.611  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.732      ;
; 0.611  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.732      ;
; 0.612  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.733      ;
; 0.612  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.733      ;
; 0.622  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.743      ;
; 0.624  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.745      ;
; 0.625  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.746      ;
; 0.625  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.746      ;
; 0.628  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.749      ;
; 0.635  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.756      ;
; 0.647  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.768      ;
; 0.648  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.769      ;
; 0.648  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.769      ;
; 0.649  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.770      ;
; 0.658  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.780      ;
; 0.659  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.780      ;
; 0.659  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.781      ;
; 0.659  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.781      ;
; 0.659  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.781      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.781      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.781      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.781      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.038      ; 0.782      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.781      ;
; 0.660  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.781      ;
; 0.661  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.782      ;
; 0.661  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.782      ;
; 0.674  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.795      ;
; 0.674  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.795      ;
; 0.677  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.798      ;
; 0.677  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.798      ;
; 0.678  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.799      ;
; 0.738  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.859      ;
; 0.738  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.859      ;
; 0.739  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.860      ;
; 0.762  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.883      ;
; 0.763  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.884      ;
; 0.765  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.886      ;
; 0.766  ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0]       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4                                                                      ; SW_USER4    ; 0.000        ; 0.037      ; 0.887      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; -0.379 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.089      ;
; 0.192  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.314      ;
; 0.193  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.275  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.060      ;
; 0.296  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.418      ;
; 0.296  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.418      ;
; 0.296  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.418      ;
; 0.297  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.419      ;
; 0.298  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.420      ;
; 0.299  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.301  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.423      ;
; 0.304  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.304  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.307  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.429      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.340  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.323      ;
; 0.435  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.384      ; 1.903      ;
; 0.445  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.567      ;
; 0.445  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.567      ;
; 0.446  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.567      ;
; 0.447  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.568      ;
; 0.454  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.576      ;
; 0.455  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.577      ;
; 0.456  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.578      ;
; 0.457  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.579      ;
; 0.458  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.458  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.580      ;
; 0.459  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.459  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.581      ;
; 0.460  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.462  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.584      ;
; 0.469  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.701      ; 1.254      ;
; 0.508  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.630      ;
; 0.508  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.630      ;
; 0.509  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.510  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.631      ;
; 0.511  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.633      ;
; 0.513  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.634      ;
; 0.520  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.642      ;
; 0.521  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.642      ;
; 0.521  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.643      ;
; 0.522  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.643      ;
; 0.523  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.644      ;
; 0.523  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.645      ;
; 0.525  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.646      ;
; 0.525  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.647      ;
; 0.526  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.647      ;
; 0.528  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.650      ;
; 0.574  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.696      ;
; 0.576  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.697      ;
; 0.586  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.708      ;
; 0.588  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.709      ;
; 0.589  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.710      ;
; 0.591  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.713      ;
; 0.605  ; SW_USER3                                                                                  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3                                                                      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.227      ; 1.946      ;
; 0.654  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.022      ; 0.760      ;
; 0.693  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.693  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.693  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.693  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.693  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.716  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.022      ; 0.822      ;
; 0.742  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.863      ;
; 0.742  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.863      ;
; 0.799  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.920      ;
; 0.803  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.925      ;
; 0.803  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.925      ;
; 0.803  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.925      ;
; 0.803  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.925      ;
; 0.803  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.925      ;
; 0.811  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.933      ;
; 0.811  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.933      ;
; 0.815  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.936      ;
; 0.815  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.936      ;
; 0.815  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.936      ;
; 0.815  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.936      ;
; 0.815  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.936      ;
+--------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                             ; To Node                                                                                                          ; Launch Clock                                                                     ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -0.297 ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0]                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.380      ; 1.187      ;
; -0.203 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z                                    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.868      ; 1.874      ;
; -0.185 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.868      ; 1.872      ;
; -0.134 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.873      ; 1.928      ;
; -0.112 ; JTAG_NEXUS_TCK                                                                                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck1_Z                                                                          ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.873      ; 1.875      ;
; 0.014  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.874      ; 2.077      ;
; 0.014  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.874      ; 2.077      ;
; 0.152  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.684      ;
; 0.154  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.686      ;
; 0.184  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.714      ;
; 0.192  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.314      ;
; 0.192  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                                      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.314      ;
; 0.193  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                                                  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.315      ;
; 0.206  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.730      ;
; 0.211  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.419      ; 0.744      ;
; 0.217  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.749      ;
; 0.220  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.752      ;
; 0.220  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.752      ;
; 0.221  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.745      ;
; 0.222  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.754      ;
; 0.226  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.221      ; 0.551      ;
; 0.237  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.769      ;
; 0.239  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.771      ;
; 0.244  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_8__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.776      ;
; 0.245  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.777      ;
; 0.247  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.779      ;
; 0.263  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_1__Z                                                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.385      ;
; 0.267  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_3__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.389      ;
; 0.269  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.801      ;
; 0.270  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.802      ;
; 0.273  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.234      ; 0.611      ;
; 0.276  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.808      ;
; 0.278  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck2_Z                                                                                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|tck3_Z                                                                          ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.400      ;
; 0.280  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.812      ;
; 0.282  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_0__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.415      ; 0.811      ;
; 0.282  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.814      ;
; 0.286  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.818      ;
; 0.288  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.820      ;
; 0.288  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.820      ;
; 0.290  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.235      ; 0.629      ;
; 0.290  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.235      ; 0.629      ;
; 0.292  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.414      ;
; 0.296  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z                                                                     ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.221      ; 0.621      ;
; 0.299  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.421      ;
; 0.300  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.832      ;
; 0.301  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.831      ;
; 0.301  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.833      ;
; 0.303  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.835      ;
; 0.305  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.837      ;
; 0.310  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z                                                ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 0.837      ;
; 0.310  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z                                                                      ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a0~porta_datain_reg0  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.234      ; 0.648      ;
; 0.315  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_5__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.437      ;
; 0.316  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.840      ;
; 0.317  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.849      ;
; 0.319  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.851      ;
; 0.319  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.851      ;
; 0.323  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.855      ;
; 0.323  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.855      ;
; 0.323  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.224      ; 0.651      ;
; 0.324  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.407      ; 0.845      ;
; 0.324  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.856      ;
; 0.338  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.460      ;
; 0.342  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.464      ;
; 0.346  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.468      ;
; 0.347  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.871      ;
; 0.349  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z                                                        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.470      ;
; 0.352  ; SW_USER4                                                                                                                              ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z                                    ; SW_USER4                                                                         ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.868      ; 2.334      ;
; 0.359  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.480      ;
; 0.359  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z                                                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_0__Z                                                ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.481      ;
; 0.361  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_1__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.483      ;
; 0.362  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.483      ;
; 0.363  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.887      ;
; 0.365  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.897      ;
; 0.365  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_9__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.487      ;
; 0.368  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.900      ;
; 0.368  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.900      ;
; 0.371  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff_Z                                                                                           ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|clken_ff1_Z                                                                     ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.039      ; 0.494      ;
; 0.372  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.376  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.908      ;
; 0.377  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.901      ;
; 0.377  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.498      ;
; 0.379  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|rst_Z                                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|tmp_Z                                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.501      ;
; 0.380  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z                                                         ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z                                        ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.501      ;
; 0.381  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a6~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.238      ; 0.723      ;
; 0.382  ; SW_USER4                                                                                                                              ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z                                    ; SW_USER4                                                                         ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.868      ; 2.364      ;
; 0.383  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.915      ;
; 0.383  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 0.907      ;
; 0.389  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.921      ;
; 0.392  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z                                                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z                                               ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.514      ;
; 0.394  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.221      ; 0.719      ;
; 0.398  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_2__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_2__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.041      ; 0.523      ;
; 0.398  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z                                                                  ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a4~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.232      ; 0.734      ;
; 0.401  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|rst_Z                                                        ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.417      ; 0.932      ;
; 0.401  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z                                             ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.933      ;
; 0.401  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z                                                                     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z                                            ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.523      ;
; 0.403  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_3__Z                                                             ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z                                                 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.524      ;
; 0.408  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startpos_1_8__Z                                                                   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_8__Z                                             ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.530      ;
; 0.419  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_nxt_0__Z                                               ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.951      ;
; 0.427  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z                                              ; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.418      ; 0.959      ;
; 0.427  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_10__Z                                                                 ; memory_u10:U10_U2|altsyncram:altsyncram_component|altsyncram_h681:auto_generated|ram_block1a2~porta_address_reg0 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.224      ; 0.755      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                               ; To Node                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.185 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.191 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_15__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_14__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_4__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.192 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.203 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.324      ;
; 0.203 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_3__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.325      ;
; 0.203 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_0__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.325      ;
; 0.204 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_2__Z                                 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|sh_ireg_1__Z                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.326      ;
; 0.206 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_7__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.327      ;
; 0.234 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.356      ;
; 0.239 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.361      ;
; 0.242 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.364      ;
; 0.255 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_6__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.377      ;
; 0.264 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_24__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.386      ;
; 0.264 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.386      ;
; 0.264 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.386      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_16__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_9__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_8__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.265 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|up_reg_7__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_7__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.387      ;
; 0.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_20__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.388      ;
; 0.266 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.388      ;
; 0.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_26__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_25__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.389      ;
; 0.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_18__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_17__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.389      ;
; 0.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.389      ;
; 0.271 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.393      ;
; 0.272 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|up_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.394      ;
; 0.274 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.396      ;
; 0.275 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_4__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.397      ;
; 0.275 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.397      ;
; 0.275 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.397      ;
; 0.276 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.398      ;
; 0.276 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.398      ;
; 0.276 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.398      ;
; 0.276 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.398      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.398      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_1__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_1__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_0__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.277 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_3__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_2__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.399      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.399      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.399      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_3__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_1:U_TRWORD2REG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_3:U_ECNTREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.278 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.400      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_7__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2:U_TRWORDREG|sh_reg_6__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_7__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.279 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.401      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.401      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.401      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.401      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.418      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_4__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.402      ;
; 0.280 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.236      ; 0.600      ;
; 0.286 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.044      ; 0.414      ;
; 0.287 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.425      ;
; 0.290 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.044      ; 0.418      ;
; 0.294 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_1__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_0__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.416      ;
; 0.294 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.044      ; 0.422      ;
; 0.295 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_6__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_5__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.417      ;
; 0.301 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.044      ; 0.429      ;
; 0.301 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.044      ; 0.429      ;
; 0.302 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_3__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|up_reg_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.236      ; 0.622      ;
; 0.306 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.043      ; 0.433      ;
; 0.309 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.043      ; 0.436      ;
; 0.309 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.043      ; 0.436      ;
; 0.330 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.452      ;
; 0.331 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.453      ;
; 0.331 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                            ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|shiftdr_r_Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.425      ; 0.360      ;
; 0.333 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_21__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.455      ;
; 0.334 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_1__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.455      ;
; 0.334 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_23__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_22__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.456      ;
; 0.335 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_5__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.456      ;
; 0.335 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_4__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_3__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.457      ;
; 0.336 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_4__Z                               ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.457      ;
; 0.336 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_30__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|LAX_CFG8_DRNOOUT:id_reg_unit|sh_reg_29__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.458      ;
; 0.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.459      ;
; 0.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z        ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.459      ;
; 0.337 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_5__Z     ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_4:U_SELREG|sh_reg_4__Z     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.459      ;
; 0.338 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z    ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.459      ;
; 0.338 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_5__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.460      ;
; 0.338 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_1__Z  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ2_2:U_TRMASKREG|sh_reg_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.460      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SW_USER2'                                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                            ; To Node                                                                                              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.208 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.022      ; 0.314      ;
; 0.372 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.480      ;
; 0.465 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.573      ;
; 0.469 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.577      ;
; 0.470 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.578      ;
; 0.471 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.579      ;
; 0.472 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.580      ;
; 0.472 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.580      ;
; 0.476 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.584      ;
; 0.476 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.584      ;
; 0.517 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.625      ;
; 0.523 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.631      ;
; 0.531 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.639      ;
; 0.532 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.640      ;
; 0.557 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.665      ;
; 0.557 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.665      ;
; 0.560 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.668      ;
; 0.581 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.689      ;
; 0.585 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.693      ;
; 0.586 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.694      ;
; 0.592 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.700      ;
; 0.592 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.700      ;
; 0.605 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.713      ;
; 0.605 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.713      ;
; 0.608 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.716      ;
; 0.620 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.728      ;
; 0.621 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.729      ;
; 0.622 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.730      ;
; 0.623 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.731      ;
; 0.626 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.734      ;
; 0.627 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.735      ;
; 0.629 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.737      ;
; 0.633 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.741      ;
; 0.633 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.741      ;
; 0.633 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.741      ;
; 0.633 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.741      ;
; 0.634 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.742      ;
; 0.634 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.742      ;
; 0.639 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.747      ;
; 0.650 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.758      ;
; 0.653 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.761      ;
; 0.670 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.778      ;
; 0.670 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.778      ;
; 0.675 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.783      ;
; 0.676 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.784      ;
; 0.680 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.788      ;
; 0.681 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.789      ;
; 0.724 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.832      ;
; 0.725 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.833      ;
; 0.760 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.868      ;
; 0.760 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.868      ;
; 0.763 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.871      ;
; 0.769 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.877      ;
; 0.770 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.878      ;
; 0.873 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.981      ;
; 0.879 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.987      ;
; 0.880 ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER2     ; SW_USER2    ; 0.000        ; 0.024      ; 0.988      ;
+-------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.303 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.425      ;
; 0.303 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.425      ;
; 0.305 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.427      ;
; 0.305 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.427      ;
; 0.305 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.427      ;
; 0.306 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.428      ;
; 0.308 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.429      ;
; 0.309 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.430      ;
; 0.315 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.436      ;
; 0.316 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.437      ;
; 0.317 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.438      ;
; 0.317 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.438      ;
; 0.361 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.482      ;
; 0.362 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.484      ;
; 0.363 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.485      ;
; 0.369 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.491      ;
; 0.369 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.491      ;
; 0.369 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.491      ;
; 0.371 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.493      ;
; 0.374 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.496      ;
; 0.374 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.496      ;
; 0.374 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.495      ;
; 0.375 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.496      ;
; 0.375 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.496      ;
; 0.376 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.497      ;
; 0.383 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.504      ;
; 0.452 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.574      ;
; 0.452 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.574      ;
; 0.457 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.578      ;
; 0.463 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.585      ;
; 0.463 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.585      ;
; 0.464 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.586      ;
; 0.466 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.588      ;
; 0.466 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.588      ;
; 0.467 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.589      ;
; 0.467 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.588      ;
; 0.468 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.046      ; 0.598      ;
; 0.469 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.045      ; 0.598      ;
; 0.470 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.591      ;
; 0.475 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.596      ;
; 0.476 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.597      ;
; 0.478 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.599      ;
; 0.510 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.631      ;
; 0.511 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.633      ;
; 0.512 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.634      ;
; 0.515 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.637      ;
; 0.515 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.637      ;
; 0.518 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.640      ;
; 0.518 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.640      ;
; 0.518 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.640      ;
; 0.520 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.641      ;
; 0.523 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.645      ;
; 0.523 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.645      ;
; 0.523 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.644      ;
; 0.523 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.644      ;
; 0.524 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.645      ;
; 0.525 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.646      ;
; 0.527 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.649      ;
; 0.527 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.649      ;
; 0.528 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.048      ; 0.660      ;
; 0.529 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.651      ;
; 0.529 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.651      ;
; 0.530 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.652      ;
; 0.530 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.652      ;
; 0.530 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.652      ;
; 0.532 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.654      ;
; 0.532 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.654      ;
; 0.533 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.655      ;
; 0.533 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.654      ;
; 0.533 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.654      ;
; 0.534 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.655      ;
; 0.536 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.657      ;
; 0.536 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.657      ;
; 0.537 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.658      ;
; 0.541 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.036      ; 0.661      ;
; 0.541 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.662      ;
; 0.542 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.036      ; 0.662      ;
; 0.544 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.665      ;
; 0.547 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.036      ; 0.667      ;
; 0.551 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.036      ; 0.671      ;
; 0.557 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.679      ;
; 0.558 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.679      ;
; 0.573 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.694      ;
; 0.574 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.696      ;
; 0.575 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.697      ;
; 0.576 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.697      ;
; 0.577 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.699      ;
; 0.578 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.700      ;
; 0.581 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.703      ;
; 0.581 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.703      ;
; 0.581 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.703      ;
; 0.583 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.036      ; 0.703      ;
; 0.584 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.706      ;
; 0.584 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.706      ;
; 0.584 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.706      ;
; 0.586 ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.038      ; 0.708      ;
; 0.586 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.707      ;
; 0.586 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.707      ;
; 0.587 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]  ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.708      ;
; 0.588 ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ; CLK_BRD      ; CLK_BRD     ; 0.000        ; 0.037      ; 0.709      ;
+-------+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                         ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -1.392 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 0.488      ; 2.357      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.715 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.786      ; 2.978      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.664 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.784      ; 2.925      ;
; -0.372 ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.488      ; 1.837      ;
; -0.022 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.500        ; 1.168      ; 1.667      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.376  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.786      ; 2.387      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.392  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.784      ; 2.369      ;
; 0.895  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 1.168      ; 1.250      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -0.727 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.788      ;
; -0.727 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.788      ;
; -0.727 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.788      ;
; -0.727 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.788      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.683 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.613      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.637 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.572      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.549 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.479      ;
; -0.541 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.476      ;
; -0.541 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.476      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.503 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.438      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.475 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.405      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.450 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 1.380      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.429 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.364      ;
; -0.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.342      ;
; -0.407 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.342      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.404 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.339      ;
; -0.333 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.268      ;
; -0.333 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.268      ;
; -0.308 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.243      ;
; -0.308 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 1.243      ;
+--------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                    ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.314 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.565      ;
; -0.229 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.476      ;
; -0.214 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.461      ;
; -0.214 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.461      ;
; -0.211 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.459      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.428      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.428      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.180 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.431      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.172 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.423      ;
; -0.161 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.409      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.106 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.357      ;
; -0.095 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.342      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.081 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.332      ;
; -0.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.327      ;
; -0.080 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.327      ;
; -0.077 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.325      ;
; -0.046 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.294      ;
; -0.046 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.294      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.040 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.291      ;
; -0.028 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.276      ;
; -0.021 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.268      ;
; -0.006 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.253      ;
; -0.006 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.253      ;
; -0.003 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.251      ;
; 0.004  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.243      ;
; 0.019  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.228      ;
; 0.019  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.270      ; 1.228      ;
; 0.022  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.226      ;
; 0.028  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.220      ;
; 0.028  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.220      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.036  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.215      ;
; 0.047  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.201      ;
; 0.053  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.195      ;
; 0.053  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.195      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.061  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.274      ; 1.190      ;
; 0.072  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.271      ; 1.176      ;
; 0.107  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 1.147      ;
; 0.107  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 1.147      ;
; 0.210  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 1.044      ;
; 0.210  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 1.044      ;
; 0.296  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 0.958      ;
; 0.296  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 0.958      ;
; 0.340  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 0.914      ;
; 0.340  ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.277      ; 0.914      ;
+--------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                          ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node                                                                                   ; Launch Clock ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.133 ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.227      ; 1.208      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.299  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.869      ; 2.282      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.314  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.872      ; 2.300      ;
; 0.780  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.227      ; 1.621      ;
; 1.139  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.519      ; 1.772      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.344  ; SW_USER3  ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER3     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.869      ; 2.827      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 1.394  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 1.872      ; 2.880      ;
; 2.150  ; SW_USER4  ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ; SW_USER4     ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.500       ; 0.519      ; 2.283      ;
+--------+-----------+-------------------------------------------------------------------------------------------+--------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                            ; Launch Clock   ; Latch Clock                                                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+
; 0.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.797      ;
; 0.267 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.797      ;
; 0.350 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.880      ;
; 0.350 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.880      ;
; 0.421 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.951      ;
; 0.421 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.951      ;
; 0.458 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.988      ;
; 0.458 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.416      ; 0.988      ;
; 0.497 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.021      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.508 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.035      ;
; 0.514 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.038      ;
; 0.514 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.038      ;
; 0.529 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.053      ;
; 0.531 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.053      ;
; 0.531 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.053      ;
; 0.548 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.409      ; 1.071      ;
; 0.592 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.116      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.603 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.130      ;
; 0.609 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.133      ;
; 0.609 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.133      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.621 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.148      ;
; 0.624 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.148      ;
; 0.626 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.148      ;
; 0.626 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.148      ;
; 0.643 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.409      ; 1.166      ;
; 0.675 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.199      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.686 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.213      ;
; 0.688 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.212      ;
; 0.692 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.216      ;
; 0.692 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.216      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.699 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_11__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.226      ;
; 0.705 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.229      ;
; 0.705 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.229      ;
; 0.707 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.231      ;
; 0.709 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.231      ;
; 0.709 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.231      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.716 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.243      ;
; 0.720 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.410      ; 1.244      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.244      ;
; 0.722 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.408      ; 1.244      ;
; 0.726 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.409      ; 1.249      ;
; 0.739 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.409      ; 1.262      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.799 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.326      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
; 0.812 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.413      ; 1.339      ;
+-------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+----------------+----------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                                                                                            ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.941 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.071      ;
; 0.941 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.071      ;
; 1.036 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.166      ;
; 1.036 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.166      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.041 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.171      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.059 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.184      ;
; 1.119 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.249      ;
; 1.119 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.249      ;
; 1.132 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.262      ;
; 1.132 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.262      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.136 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.266      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.154 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.279      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.219 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.349      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.232 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.046      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.237 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.362      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.250 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.375      ;
; 1.423 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_1__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; -0.349     ; 0.678      ;
; 1.423 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_3__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; -0.349     ; 0.678      ;
; 1.423 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; -0.349     ; 0.678      ;
; 1.423 ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|reset_r_Z      ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_TAPCONTROLLER:U_TAP|up_ireg_2__Z                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; -0.349     ; 0.678      ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                                                                                        ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                                                                                        ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                                                                                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_0__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_1__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_2__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_3__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_4__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_5__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_6__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_BUFFREG:U_BUFFREG|sh_reg_7__Z                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_0__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_1__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_2__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_3__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_4__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_5__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_6__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|sh_reg_7__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_0__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_1__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_2__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_3__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_4__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_5__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_6__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CFGREG:U_CFGREG|up_reg_7__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_0__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_1__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|sh_reg_2__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_0__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_CTRLREG:U_CTRLREG|up_reg_1__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_0__Z ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_10__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_11__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_12__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_13__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_14__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_15__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_3__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_4__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_5__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_6__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_7__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_8__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|sh_reg_9__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_10__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_11__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_12__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_13__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_14__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_15__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_3__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_4__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_5__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_6__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_7__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_8__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ0:U_MAGNITREG|up_reg_9__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_10__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_11__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_12__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_13__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_14__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_15__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_16__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_17__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_18__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_19__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_20__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_3__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_4__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_5__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_6__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_7__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_8__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|sh_reg_9__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_10__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_11__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_12__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_13__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_14__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_15__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_16__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_17__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_18__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_19__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_20__Z         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_LA16PORT:U_LA16PORT|LAX_CFG8_NXMODULE:U_NX_MODULE|LAX_CFG8_NXREGZ1:U_CURSORREG|up_reg_3__Z          ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                 ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK_BRD ; Rise       ; CLK_BRD                                                                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; -0.083 ; 0.101        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]          ;
; -0.082 ; 0.102        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_0|lpm_ff:ff1|dffs[0]       ;
; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]      ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]      ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]      ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]       ;
; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]       ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_11|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_12|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_13|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_14|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_15|lpm_ff:ff1|dffs[0]         ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_1|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_2|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_3|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_4|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_5|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_6|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_7|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_8|lpm_ff:ff1|dffs[0]          ;
; -0.054 ; 0.130        ; 0.184          ; Low Pulse Width  ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_9|lpm_ff:ff1|dffs[0]          ;
; 0.097  ; 0.097        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_0|ff1|dffs[0]|clk                                                       ;
; 0.098  ; 0.098        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_0|ff1|dffs[0]|clk                                                       ;
; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~input|o                                                                  ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|clk                                                 ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|INST_CLKOUT|ff1|dffs[0]|clk                                                 ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_10|ff1|dffs[0]|clk                                                      ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_11|ff1|dffs[0]|clk                                                      ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_12|ff1|dffs[0]|clk                                                      ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_1|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_2|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_3|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_4|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_5|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_6|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_7|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_8|ff1|dffs[0]|clk                                                       ;
; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U902|cnt_9|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_10|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_11|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_12|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_13|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_14|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_15|ff1|dffs[0]|clk                                                      ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_1|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_2|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_3|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_4|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_5|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_6|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_7|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_8|ff1|dffs[0]|clk                                                       ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; U901|cnt_9|ff1|dffs[0]|clk                                                       ;
; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|inclk[0]                                                    ;
; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~inputclkctrl|outclk                                                      ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK_BRD ; Rise       ; CLK_BRD~input|i                                                                  ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK_BRD ; Rise       ; CLK_BRD~input|i                                                                  ;
; 0.653  ; 0.869        ; 0.216          ; High Pulse Width ; CLK_BRD ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:cnt_10|lpm_ff:ff1|dffs[0]         ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER3'                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER3 ; Rise       ; SW_USER3                                                                                           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; -0.097 ; 0.119        ; 0.216          ; High Pulse Width ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; 0.005  ; 0.005        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
; 0.011  ; 0.011        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.116  ; 0.116        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.116  ; 0.116        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.125  ; 0.125        ; 0.000          ; High Pulse Width ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Rise       ; SW_USER3~input|i                                                                                   ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_1|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_2|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_3|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_4|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_5|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_6|lpm_ff:ff1|dffs[0]      ;
; 0.694  ; 0.878        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_7|lpm_ff:ff1|dffs[0]      ;
; 0.695  ; 0.879        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:INST_PWM|lpm_ff:ff1|dffs[0] ;
; 0.695  ; 0.879        ; 0.184          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Configurable_U11:LED_Brightness_U11|Epson__AltSyn_AltiumAlteraDffAsync:I_0|lpm_ff:ff1|dffs[0]      ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_1|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_2|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_3|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_4|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_5|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_6|ff1|dffs[0]|clk                                                             ;
; 0.874  ; 0.874        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_7|ff1|dffs[0]|clk                                                             ;
; 0.875  ; 0.875        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|INST_PWM|ff1|dffs[0]|clk                                                        ;
; 0.875  ; 0.875        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; LED_Brightness_U11|I_0|ff1|dffs[0]|clk                                                             ;
; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; SW_USER3~input|o                                                                                   ;
; 0.884  ; 0.884        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|inclk[0]                                                                        ;
; 0.884  ; 0.884        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O~clkctrl|outclk                                                                          ;
; 0.985  ; 0.985        ; 0.000          ; High Pulse Width ; SW_USER3 ; Rise       ; Deb02_U4|O_x|datad                                                                                 ;
; 0.990  ; 0.990        ; 0.000          ; Low Pulse Width  ; SW_USER3 ; Fall       ; Deb02_U4|O_x|combout                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER4'                                                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                              ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER4 ; Rise       ; SW_USER4                                                                            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -0.127 ; 0.089        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -0.126 ; 0.090        ; 0.216          ; High Pulse Width ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -0.016 ; -0.016       ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
; -0.010 ; -0.010       ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
; 0.085  ; 0.085        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.085  ; 0.085        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.095  ; 0.095        ; 0.000          ; High Pulse Width ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Rise       ; SW_USER4~input|i                                                                    ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.725  ; 0.909        ; 0.184          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Configurable_U9:U9|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; SW_USER4~input|o                                                                    ;
; 0.904  ; 0.904        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.905  ; 0.905        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; U9|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.914  ; 0.914        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|inclk[0]                                                         ;
; 0.914  ; 0.914        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O~clkctrl|outclk                                                           ;
; 1.006  ; 1.006        ; 0.000          ; High Pulse Width ; SW_USER4 ; Rise       ; Deb01_U4|O_x|datad                                                                  ;
; 1.011  ; 1.011        ; 0.000          ; Low Pulse Width  ; SW_USER4 ; Fall       ; Deb01_U4|O_x|combout                                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SW_USER2'                                                                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; SW_USER2 ; Rise       ; SW_USER2                                                                                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -0.080 ; 0.104        ; 0.184          ; Low Pulse Width  ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.099  ; 0.099        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; SW_USER2 ; Rise       ; SW_USER2~input|i                                                                                     ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.679  ; 0.895        ; 0.216          ; High Pulse Width ; SW_USER2 ; Rise       ; Configurable_U12:LED_Brightness_U12|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; SW_USER2~input|o                                                                                     ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_0|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_1|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_2|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_3|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_4|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_5|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_6|ff1|dffs[0]|clk                                                          ;
; 0.900  ; 0.900        ; 0.000          ; High Pulse Width ; SW_USER2 ; Rise       ; LED_Brightness_U12|INST_Q_7|ff1|dffs[0]|clk                                                          ;
+--------+--------------+----------------+------------------+----------+------------+------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                         ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                                                                            ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_3__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_4__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_5__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_6__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Fall       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|buffregout_7__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_0__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|dstate_1__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_0__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_10__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_11__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_1__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_2__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_3__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_4__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_5__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_6__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_7__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_8__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|memrdaddr_9__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_DUMP:U_DUMP|startcap_s_Z             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|bf_Z                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_0__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_10__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_11__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_12__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_13__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_14__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_15__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_16__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_17__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_18__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_19__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_1__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_20__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_2__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_3__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_4__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_5__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_6__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_7__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_8__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|capturecnt_9__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_0__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_1__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_cap_2__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow0_trig_3__Z ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_0__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_1__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_cap_2__Z  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow1_trig_3__Z ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_0__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_1__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_2__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow2_3__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_0__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_1__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_2__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|channels_shadow3_3__Z      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_0__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_1__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_2__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_3__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_4__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_5__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_6__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_7__Z              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_0__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_1__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_2__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_3__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_4__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_5__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_6__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|curevcnt_nxt_7__Z          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_0__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_10__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_11__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_12__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_13__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_14__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_15__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_16__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_17__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_18__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_19__Z           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_1__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_2__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_3__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_4__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_5__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_6__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_7__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_8__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|cursormask_9__Z            ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|la_status_Z                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_0__Z               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; LAX_CFG8:U10_U1|LAX_CFG8_LA16:U1|LAX_CFG8_FSM:U_FSM|memaddr_10__Z              ;
+--------+--------------+----------------+------------+----------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.201  ; 0.385        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.267  ; 0.451        ; 0.184          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.329  ; 0.545        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.331  ; 0.331        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.381  ; 0.381        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.383  ; 0.383        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.391  ; 0.391        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.391  ; 0.391        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb01_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_0|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_1|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_2|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_3|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_4|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_5|lpm_ff:ff1|dffs[0] ;
; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_6|lpm_ff:ff1|dffs[0] ;
; 0.440  ; 0.656        ; 0.216          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Configurable_U2:Deb02_U2|Epson__AltSyn_AltiumAlteraDffAsyncEn:INST_Q_7|lpm_ff:ff1|dffs[0] ;
; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]|q                                                            ;
; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
; 0.605  ; 0.605        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|inclk[0]                                             ;
; 0.605  ; 0.605        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; U901|INST_CLKOUT|ff1|dffs[0]~clkctrl|outclk                                               ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb01_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_0|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_1|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_2|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_3|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_4|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_5|ff1|dffs[0]|clk                                                         ;
; 0.614  ; 0.614        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_6|ff1|dffs[0]|clk                                                         ;
; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; Rise       ; Deb02_U2|INST_Q_7|ff1|dffs[0]|clk                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.182  ; 0.460  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.673  ; 1.217  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 0.776  ; 1.243  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 1.448  ; 1.957  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; 1.607  ; 2.352  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; 1.547  ; 2.247  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; 1.193  ; 1.758  ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 0.003  ; 0.540  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; -0.868 ; -0.239 ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; -0.674 ; 0.015  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; -0.060 ; 0.540  ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; -0.538 ; 0.126  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; -0.869 ; -0.227 ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; -0.443 ; 0.199  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; -0.018 ; 0.540  ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.003  ; 0.486  ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; -0.648 ; -0.317 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                          ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.082  ; -0.183 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.382 ; -0.847 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.370 ; -0.808 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.207 ; -1.559 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; -0.989 ; -1.665 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; -1.276 ; -1.992 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; -0.920 ; -1.466 ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 1.243  ; 0.615  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; 1.243  ; 0.615  ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; 1.002  ; 0.326  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.414  ; -0.177 ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; 0.871  ; 0.218  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; 1.189  ; 0.558  ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; 0.779  ; 0.150  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.373  ; -0.177 ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.353  ; -0.125 ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; 1.008  ; 0.694  ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                             ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 5.099 ; 5.378 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 5.099 ; 5.378 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.343 ; 3.493 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.343 ; 3.493 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 4.266 ; 4.469 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 4.266 ; 4.469 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.577 ; 3.751 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 8.178 ; 8.499 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 4.584 ; 4.248 ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 4.584 ; 4.248 ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 6.728 ; 6.977 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 6.378 ; 6.525 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 6.728 ; 6.977 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 5.934 ; 6.009 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 6.440 ; 6.596 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 8.248 ; 8.670 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 7.747 ; 8.066 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 7.509 ; 7.802 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 8.158 ; 8.605 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 8.248 ; 8.670 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 6.832 ; 7.035 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 7.143 ; 7.409 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 6.003 ; 6.089 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 6.404 ; 6.544 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 8.772 ; 9.240 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 8.276 ; 8.684 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 7.745 ; 8.083 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 8.608 ; 9.058 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 8.618 ; 9.032 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 8.037 ; 8.453 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 8.772 ; 9.240 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 8.719 ; 9.166 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 6.750 ; 6.915 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.477 ; 5.056 ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.438 ; 5.056 ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.477 ; 4.068 ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 5.178 ; 4.671 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.178 ; 4.671 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.711 ; 4.326 ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.477 ; 5.056 ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.438 ; 5.056 ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.477 ; 4.068 ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 5.178 ; 4.671 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.178 ; 4.671 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.711 ; 4.326 ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 8.113 ; 8.433 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 7.119 ; 7.333 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 7.949 ; 8.260 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 7.615 ; 7.895 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 8.113 ; 8.433 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 6.932 ; 7.157 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 7.679 ; 7.961 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 7.623 ; 7.889 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 7.114 ; 7.319 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 6.528 ; 6.673 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 6.528 ; 6.673 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 6.398 ; 6.509 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 5.952 ; 6.010 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 5.952 ; 6.017 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                     ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4.941 ; 5.208 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4.941 ; 5.208 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.263 ; 3.407 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.263 ; 3.407 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.488 ; 3.655 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 4.150 ; 4.344 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.488 ; 3.655 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 4.636 ; 4.884 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 6.198 ; 6.339 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 6.534 ; 6.772 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 6.259 ; 6.395 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 5.844 ; 5.927 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 7.520 ; 7.825 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 7.276 ; 7.542 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 7.932 ; 8.357 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 7.987 ; 8.381 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 6.620 ; 6.799 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 6.919 ; 7.164 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 5.844 ; 5.927 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 6.229 ; 6.364 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 6.562 ; 6.720 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 8.026 ; 8.417 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 7.516 ; 7.841 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 8.345 ; 8.778 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 8.354 ; 8.752 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 7.790 ; 8.189 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 8.496 ; 8.946 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 8.447 ; 8.877 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 6.562 ; 6.720 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.332 ; 3.979 ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.332 ; 4.942 ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.387 ; 3.979 ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.053 ; 4.549 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.332 ; 3.979 ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.332 ; 4.942 ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.387 ; 3.979 ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.053 ; 4.549 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 6.730 ; 6.947 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 6.916 ; 7.122 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 7.706 ; 7.997 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 7.393 ; 7.663 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 7.872 ; 8.179 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 6.730 ; 6.947 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 7.447 ; 7.719 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 7.396 ; 7.652 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 6.887 ; 7.073 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 5.791 ; 5.846 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 6.344 ; 6.482 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 6.219 ; 6.325 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 5.791 ; 5.846 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 5.792 ; 5.853 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; HA[12]     ; LED_G[0]    ;    ; 5.771 ; 6.227 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 5.259 ; 5.710 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 6.061 ; 6.417 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 6.032 ; 6.428 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 4.485 ; 5.014 ;    ;
; HA[17]     ; LED_G[5]    ;    ; 4.967 ; 5.551 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 4.103 ; 4.729 ;    ;
; HA[19]     ; LED_G[7]    ;    ; 4.011 ; 4.574 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; HA[12]     ; LED_G[0]    ;    ; 5.610 ; 6.065 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 5.118 ; 5.567 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 5.928 ; 6.280 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 5.863 ; 6.259 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 4.369 ; 4.893 ;    ;
; HA[17]     ; LED_G[5]    ;    ; 4.832 ; 5.409 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 4.009 ; 4.626 ;    ;
; HA[19]     ; LED_G[7]    ;    ; 3.922 ; 4.479 ;    ;
+------------+-------------+----+-------+-------+----+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                ;
+-----------------------------------------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Clock                                                                             ; Setup     ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Worst-case Slack                                                                  ; -9.795    ; -1.777  ; -2.696   ; -0.208  ; -3.201              ;
;  CLK_BRD                                                                          ; -4.398    ; 0.303   ; N/A      ; N/A     ; -3.000              ;
;  ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -9.795    ; -0.588  ; -1.723   ; 0.267   ; -3.201              ;
;  ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -5.109    ; -0.504  ; -2.514   ; -0.208  ; -1.487              ;
;  JTAG_NEXUS_TCK                                                                   ; -4.375    ; 0.185   ; -2.696   ; 0.941   ; -3.000              ;
;  SW_USER2                                                                         ; -1.888    ; 0.208   ; N/A      ; N/A     ; -3.000              ;
;  SW_USER3                                                                         ; -1.914    ; -1.777  ; N/A      ; N/A     ; -3.000              ;
;  SW_USER4                                                                         ; -1.931    ; -1.390  ; N/A      ; N/A     ; -3.000              ;
; Design-wide TNS                                                                   ; -1655.139 ; -16.883 ; -106.159 ; -0.208  ; -740.044            ;
;  CLK_BRD                                                                          ; -110.574  ; 0.000   ; N/A      ; N/A     ; -49.097             ;
;  ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -601.528  ; -1.361  ; -30.316  ; 0.000   ; -245.105            ;
;  ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -38.100   ; -3.024  ; -15.058  ; -0.208  ; -23.792             ;
;  JTAG_NEXUS_TCK                                                                   ; -866.070  ; 0.000   ; -60.785  ; 0.000   ; -374.750            ;
;  SW_USER2                                                                         ; -12.184   ; 0.000   ; N/A      ; N/A     ; -14.896             ;
;  SW_USER3                                                                         ; -13.758   ; -1.777  ; N/A      ; N/A     ; -17.508             ;
;  SW_USER4                                                                         ; -12.925   ; -10.721 ; N/A      ; N/A     ; -14.896             ;
+-----------------------------------------------------------------------------------+-----------+---------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.182  ; 0.510  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 1.898  ; 1.770  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 1.617  ; 1.822  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.297  ; 3.296  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; 3.662  ; 3.895  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; 3.541  ; 3.793  ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; 2.377  ; 2.645  ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 0.658  ; 1.138  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; -0.868 ; -0.239 ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; -0.569 ; 0.015  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.617  ; 1.068  ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; -0.346 ; 0.126  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; -0.869 ; -0.227 ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; -0.254 ; 0.212  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.658  ; 1.088  ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.598  ; 1.138  ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; -0.648 ; -0.317 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                          ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 0.558  ; 0.257  ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER4       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; -0.382 ; -0.847 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -0.370 ; -0.808 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; -1.207 ; -1.559 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK                                                                   ; -0.989 ; -1.665 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK                                                                   ; -1.276 ; -1.992 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; SW_USER1       ; SW_USER2                                                                         ; -0.920 ; -1.466 ; Rise       ; SW_USER2                                                                         ;
; SW[*]          ; SW_USER4                                                                         ; 1.837  ; 1.833  ; Fall       ; SW_USER4                                                                         ;
;  SW[0]         ; SW_USER4                                                                         ; 1.837  ; 1.833  ; Fall       ; SW_USER4                                                                         ;
;  SW[1]         ; SW_USER4                                                                         ; 1.306  ; 1.109  ; Fall       ; SW_USER4                                                                         ;
;  SW[2]         ; SW_USER4                                                                         ; 0.414  ; -0.100 ; Fall       ; SW_USER4                                                                         ;
;  SW[3]         ; SW_USER4                                                                         ; 1.092  ; 0.894  ; Fall       ; SW_USER4                                                                         ;
;  SW[4]         ; SW_USER4                                                                         ; 1.760  ; 1.508  ; Fall       ; SW_USER4                                                                         ;
;  SW[5]         ; SW_USER4                                                                         ; 1.002  ; 0.683  ; Fall       ; SW_USER4                                                                         ;
;  SW[6]         ; SW_USER4                                                                         ; 0.373  ; -0.131 ; Fall       ; SW_USER4                                                                         ;
;  SW[7]         ; SW_USER4                                                                         ; 0.353  ; -0.125 ; Fall       ; SW_USER4                                                                         ;
; SW_USER3       ; SW_USER4                                                                         ; 1.580  ; 1.350  ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                               ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 11.331 ; 11.060 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 11.331 ; 11.060 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.149  ; 7.059  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.149  ; 7.059  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.514  ; 9.301  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 9.514  ; 9.301  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 7.815  ; 7.588  ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 18.377 ; 17.887 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 9.044  ; 8.594  ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 9.044  ; 8.594  ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 14.175 ; 13.887 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 13.158 ; 12.885 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 14.175 ; 13.887 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 11.945 ; 11.845 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 13.086 ; 12.948 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 17.499 ; 17.112 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 16.366 ; 15.842 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 15.796 ; 15.422 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 16.675 ; 16.608 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 17.499 ; 17.112 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 14.410 ; 13.992 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 15.164 ; 14.732 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 12.124 ; 12.046 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 12.987 ; 12.875 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 18.826 ; 18.102 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 17.495 ; 17.144 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 16.281 ; 15.928 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 18.278 ; 17.822 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 18.379 ; 17.745 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 17.129 ; 16.670 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 18.826 ; 18.102 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 18.548 ; 18.013 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 13.918 ; 13.669 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.437  ; 8.291  ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 9.103  ; 8.820  ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 9.033  ; 9.095  ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 8.437  ; 8.291  ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 9.933  ; 9.497  ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 9.103  ; 8.820  ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 16.976 ; 16.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 14.495 ; 14.388 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 16.545 ; 16.145 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 15.764 ; 15.450 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 16.976 ; 16.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 14.304 ; 14.037 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 16.037 ; 15.500 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 15.759 ; 15.412 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 14.687 ; 14.354 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 13.392 ; 13.047 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 13.392 ; 13.047 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 13.064 ; 12.754 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 11.953 ; 11.765 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 11.985 ; 11.756 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+--------+--------+------------+----------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                     ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                       ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                  ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+
; LED_B[*]       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4.941 ; 5.208 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
;  LED_B[5]      ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4.941 ; 5.208 ; Rise       ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ;
; HB[*]          ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.263 ; 3.407 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  HB[3]         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.263 ; 3.407 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; LED_B[*]       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.488 ; 3.655 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[6]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 4.150 ; 4.344 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
;  LED_B[7]      ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 3.488 ; 3.655 ; Rise       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                   ; 4.636 ; 4.884 ; Rise       ; JTAG_NEXUS_TCK                                                                   ;
; LED_B[*]       ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Rise       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Rise       ; SW_USER3                                                                         ;
; LED_B[*]       ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[4]      ; SW_USER3                                                                         ; 6.198 ; 6.339 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[5]      ; SW_USER3                                                                         ; 6.534 ; 6.772 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[6]      ; SW_USER3                                                                         ; 4.489 ; 4.151 ; Fall       ; SW_USER3                                                                         ;
;  LED_B[7]      ; SW_USER3                                                                         ; 6.259 ; 6.395 ; Fall       ; SW_USER3                                                                         ;
; LED_G[*]       ; SW_USER3                                                                         ; 5.844 ; 5.927 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[0]      ; SW_USER3                                                                         ; 7.520 ; 7.825 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[1]      ; SW_USER3                                                                         ; 7.276 ; 7.542 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[2]      ; SW_USER3                                                                         ; 7.932 ; 8.357 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[3]      ; SW_USER3                                                                         ; 7.987 ; 8.381 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[4]      ; SW_USER3                                                                         ; 6.620 ; 6.799 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[5]      ; SW_USER3                                                                         ; 6.919 ; 7.164 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[6]      ; SW_USER3                                                                         ; 5.844 ; 5.927 ; Fall       ; SW_USER3                                                                         ;
;  LED_G[7]      ; SW_USER3                                                                         ; 6.229 ; 6.364 ; Fall       ; SW_USER3                                                                         ;
; LED_R[*]       ; SW_USER3                                                                         ; 6.562 ; 6.720 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[0]      ; SW_USER3                                                                         ; 8.026 ; 8.417 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[1]      ; SW_USER3                                                                         ; 7.516 ; 7.841 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[2]      ; SW_USER3                                                                         ; 8.345 ; 8.778 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[3]      ; SW_USER3                                                                         ; 8.354 ; 8.752 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[4]      ; SW_USER3                                                                         ; 7.790 ; 8.189 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[5]      ; SW_USER3                                                                         ; 8.496 ; 8.946 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[6]      ; SW_USER3                                                                         ; 8.447 ; 8.877 ; Fall       ; SW_USER3                                                                         ;
;  LED_R[7]      ; SW_USER3                                                                         ; 6.562 ; 6.720 ; Fall       ; SW_USER3                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.332 ; 3.979 ; Rise       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.332 ; 4.942 ; Rise       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.387 ; 3.979 ; Rise       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.053 ; 4.549 ; Rise       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Rise       ; SW_USER4                                                                         ;
; HB[*]          ; SW_USER4                                                                         ; 4.332 ; 3.979 ; Fall       ; SW_USER4                                                                         ;
;  HB[2]         ; SW_USER4                                                                         ; 4.332 ; 4.942 ; Fall       ; SW_USER4                                                                         ;
;  HB[3]         ; SW_USER4                                                                         ; 4.387 ; 3.979 ; Fall       ; SW_USER4                                                                         ;
; LED_B[*]       ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[4]      ; SW_USER4                                                                         ; 5.053 ; 4.549 ; Fall       ; SW_USER4                                                                         ;
;  LED_B[7]      ; SW_USER4                                                                         ; 4.612 ; 4.227 ; Fall       ; SW_USER4                                                                         ;
; LED_R[*]       ; SW_USER4                                                                         ; 6.730 ; 6.947 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[0]      ; SW_USER4                                                                         ; 6.916 ; 7.122 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[1]      ; SW_USER4                                                                         ; 7.706 ; 7.997 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[2]      ; SW_USER4                                                                         ; 7.393 ; 7.663 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[3]      ; SW_USER4                                                                         ; 7.872 ; 8.179 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[4]      ; SW_USER4                                                                         ; 6.730 ; 6.947 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[5]      ; SW_USER4                                                                         ; 7.447 ; 7.719 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[6]      ; SW_USER4                                                                         ; 7.396 ; 7.652 ; Fall       ; SW_USER4                                                                         ;
;  LED_R[7]      ; SW_USER4                                                                         ; 6.887 ; 7.073 ; Fall       ; SW_USER4                                                                         ;
; RELAY[*]       ; SW_USER4                                                                         ; 5.791 ; 5.846 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[0]      ; SW_USER4                                                                         ; 6.344 ; 6.482 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[1]      ; SW_USER4                                                                         ; 6.219 ; 6.325 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[2]      ; SW_USER4                                                                         ; 5.791 ; 5.846 ; Fall       ; SW_USER4                                                                         ;
;  RELAY[3]      ; SW_USER4                                                                         ; 5.792 ; 5.853 ; Fall       ; SW_USER4                                                                         ;
+----------------+----------------------------------------------------------------------------------+-------+-------+------------+----------------------------------------------------------------------------------+


+------------------------------------------------------+
; Progagation Delay                                    ;
+------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF     ; FR     ; FF ;
+------------+-------------+----+--------+--------+----+
; HA[12]     ; LED_G[0]    ;    ; 11.669 ; 12.227 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 10.660 ; 11.085 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 11.848 ; 11.963 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 12.100 ; 12.612 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 9.210  ; 9.655  ;    ;
; HA[17]     ; LED_G[5]    ;    ; 10.149 ; 10.738 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 8.465  ; 8.732  ;    ;
; HA[19]     ; LED_G[7]    ;    ; 8.032  ; 8.384  ;    ;
+------------+-------------+----+--------+--------+----+


+----------------------------------------------------+
; Minimum Progagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; HA[12]     ; LED_G[0]    ;    ; 5.610 ; 6.065 ;    ;
; HA[13]     ; LED_G[1]    ;    ; 5.118 ; 5.567 ;    ;
; HA[14]     ; LED_G[2]    ;    ; 5.928 ; 6.280 ;    ;
; HA[15]     ; LED_G[3]    ;    ; 5.863 ; 6.259 ;    ;
; HA[16]     ; LED_G[4]    ;    ; 4.369 ; 4.893 ;    ;
; HA[17]     ; LED_G[5]    ;    ; 4.832 ; 5.409 ;    ;
; HA[18]     ; LED_G[6]    ;    ; 4.009 ; 4.626 ;    ;
; HA[19]     ; LED_G[7]    ;    ; 3.922 ; 4.479 ;    ;
+------------+-------------+----+-------+-------+----+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; HB[2]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[3]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[4]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[5]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[6]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[7]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[8]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[9]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[10]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[11]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[12]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[13]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[14]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[15]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[16]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[17]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[18]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HB[19]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_B[7]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_G[7]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED_R[7]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RELAY[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RELAY[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RELAY[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RELAY[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; HA[2]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[3]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[4]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[5]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[6]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[7]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[8]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[9]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[10]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[11]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW_USER4                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW_USER3                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[12]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[13]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[14]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[15]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[16]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[17]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[18]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; HA[19]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TCK          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TMS          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TDI          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[0]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW_USER0                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[1]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[2]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[3]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[4]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[5]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[6]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW[7]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_BRD                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW_USER1                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SW_USER2                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; HB[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[10]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[11]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; HB[12]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[13]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[14]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[15]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[16]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; HB[17]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[18]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; HB[19]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.33 V              ; -0.00201 V          ; 0.092 V                              ; 0.05 V                               ; 3.78e-09 s                  ; 3.59e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.33 V             ; -0.00201 V         ; 0.092 V                             ; 0.05 V                              ; 3.78e-09 s                 ; 3.59e-09 s                 ; Yes                       ; Yes                       ;
; LED_B[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; LED_G[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; HB[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[10]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[11]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; HB[12]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[13]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[14]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[15]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[16]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; HB[17]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[18]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; HB[19]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_B[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_B[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-09 s                  ; 2.29e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-09 s                 ; 2.29e-09 s                 ; No                        ; Yes                       ;
; LED_B[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; LED_B[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_B[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_B[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_G[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_G[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_G[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; LED_G[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_G[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_G[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_G[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_R[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_R[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_R[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_R[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; LED_R[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; LED_R[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; LED_R[7]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; RELAY[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; RELAY[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                 ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                       ; To Clock                                                                         ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; CLK_BRD                                                                          ; CLK_BRD                                                                          ; 2748     ; 0        ; 0        ; 0        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 6196     ; 4        ; 24       ; 0        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 2        ; 1        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 8871     ; 1        ; 64       ; 0        ;
; SW_USER4                                                                         ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4        ; 4        ; 0        ; 0        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 200      ; 0        ; 0        ; 0        ;
; SW_USER3                                                                         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; SW_USER4                                                                         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK                                                                   ; 1        ; 8        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                   ; JTAG_NEXUS_TCK                                                                   ; 4466     ; 141      ; 12       ; 0        ;
; SW_USER2                                                                         ; SW_USER2                                                                         ; 92       ; 0        ; 0        ; 0        ;
; SW_USER2                                                                         ; SW_USER3                                                                         ; 0        ; 0        ; 16       ; 0        ;
; SW_USER3                                                                         ; SW_USER3                                                                         ; 0        ; 0        ; 0        ; 100      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; SW_USER4                                                                         ; 0        ; 0        ; 8        ; 0        ;
; SW_USER3                                                                         ; SW_USER4                                                                         ; 0        ; 0        ; 8        ; 8        ;
; SW_USER4                                                                         ; SW_USER4                                                                         ; 0        ; 0        ; 0        ; 92       ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                  ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                       ; To Clock                                                                         ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; CLK_BRD                                                                          ; CLK_BRD                                                                          ; 2748     ; 0        ; 0        ; 0        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 6196     ; 4        ; 24       ; 0        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 2        ; 1        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                   ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 8871     ; 1        ; 64       ; 0        ;
; SW_USER4                                                                         ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 4        ; 4        ; 0        ; 0        ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 200      ; 0        ; 0        ; 0        ;
; SW_USER3                                                                         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; SW_USER4                                                                         ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK                                                                   ; 1        ; 8        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                   ; JTAG_NEXUS_TCK                                                                   ; 4466     ; 141      ; 12       ; 0        ;
; SW_USER2                                                                         ; SW_USER2                                                                         ; 92       ; 0        ; 0        ; 0        ;
; SW_USER2                                                                         ; SW_USER3                                                                         ; 0        ; 0        ; 16       ; 0        ;
; SW_USER3                                                                         ; SW_USER3                                                                         ; 0        ; 0        ; 0        ; 100      ;
; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; SW_USER4                                                                         ; 0        ; 0        ; 8        ; 0        ;
; SW_USER3                                                                         ; SW_USER4                                                                         ; 0        ; 0        ; 8        ; 8        ;
; SW_USER4                                                                         ; SW_USER4                                                                         ; 0        ; 0        ; 0        ; 92       ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                            ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock     ; To Clock                                                                         ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 84       ; 0        ; 0        ; 0        ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK                                                                   ; 84       ; 4        ; 0        ; 0        ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                             ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock     ; To Clock                                                                         ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ; 84       ; 0        ; 0        ; 0        ;
; SW_USER3       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; SW_USER4       ; ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]    ; 8        ; 8        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK                                                                   ; 84       ; 4        ; 0        ; 0        ;
+----------------+----------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 22    ; 22   ;
; Unconstrained Input Port Paths  ; 55    ; 55   ;
; Unconstrained Output Ports      ; 27    ; 27   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 12.0 Build 178 05/31/2012 SJ Web Edition
    Info: Copyright (C) 1991-2012 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Mon Oct 15 23:32:55 2012
Info: Command: quartus_sta Epson --sdc=Epson_sta.sdc
Info: qsta_default_script.tcl version: #4
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Info (332104): Reading SDC File: 'Epson_sta.sdc'
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]
    Info (332105): create_clock -period 1.000 -name CLK_BRD CLK_BRD
    Info (332105): create_clock -period 1.000 -name JTAG_NEXUS_TCK JTAG_NEXUS_TCK
    Info (332105): create_clock -period 1.000 -name ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0]
    Info (332105): create_clock -period 1.000 -name SW_USER4 SW_USER4
    Info (332105): create_clock -period 1.000 -name SW_USER3 SW_USER3
    Info (332105): create_clock -period 1.000 -name SW_USER2 SW_USER2
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -9.795
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -9.795      -601.528 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -5.109       -38.100 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -4.398      -110.574 CLK_BRD 
    Info (332119):    -4.375      -866.070 JTAG_NEXUS_TCK 
    Info (332119):    -1.931       -12.925 SW_USER4 
    Info (332119):    -1.914       -13.758 SW_USER3 
    Info (332119):    -1.888       -12.184 SW_USER2 
Info (332146): Worst-case hold slack is -1.777
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.777        -1.777 SW_USER3 
    Info (332119):    -1.390       -10.721 SW_USER4 
    Info (332119):    -0.588        -1.361 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -0.504        -3.024 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.451         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.497         0.000 SW_USER2 
    Info (332119):     0.758         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -2.696
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.696       -60.785 JTAG_NEXUS_TCK 
    Info (332119):    -2.514       -15.058 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -1.723       -30.316 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info (332146): Worst-case removal slack is -0.208
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.208        -0.208 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.570         0.000 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     1.847         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case minimum pulse width slack is -3.201
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.201      -245.105 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -3.000      -374.750 JTAG_NEXUS_TCK 
    Info (332119):    -3.000       -49.097 CLK_BRD 
    Info (332119):    -3.000       -17.101 SW_USER3 
    Info (332119):    -3.000       -14.896 SW_USER2 
    Info (332119):    -3.000       -14.896 SW_USER4 
    Info (332119):    -1.487       -23.792 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -8.977
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -8.977      -559.773 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -4.593       -34.954 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -4.079      -796.833 JTAG_NEXUS_TCK 
    Info (332119):    -3.899       -98.876 CLK_BRD 
    Info (332119):    -1.672       -11.157 SW_USER4 
    Info (332119):    -1.660       -10.877 SW_USER2 
    Info (332119):    -1.639       -12.076 SW_USER3 
Info (332146): Worst-case hold slack is -1.557
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.557        -1.557 SW_USER3 
    Info (332119):    -1.269        -9.760 SW_USER4 
    Info (332119):    -0.517        -0.930 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -0.492        -2.952 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.399         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.445         0.000 SW_USER2 
    Info (332119):     0.703         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -2.485
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.485       -55.544 JTAG_NEXUS_TCK 
    Info (332119):    -2.260       -12.480 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -1.574       -27.143 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info (332146): Worst-case removal slack is -0.163
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.163        -0.163 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.494         0.000 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     1.701         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case minimum pulse width slack is -3.201
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.201      -245.105 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -3.000      -374.750 JTAG_NEXUS_TCK 
    Info (332119):    -3.000       -49.097 CLK_BRD 
    Info (332119):    -3.000       -17.508 SW_USER3 
    Info (332119):    -3.000       -14.896 SW_USER2 
    Info (332119):    -3.000       -14.896 SW_USER4 
    Info (332119):    -1.487       -23.792 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -3.522
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.522      -190.530 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -1.698       -15.596 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -1.366      -247.118 JTAG_NEXUS_TCK 
    Info (332119):    -1.317       -28.916 CLK_BRD 
    Info (332119):    -0.285        -1.216 SW_USER3 
    Info (332119):    -0.272        -1.198 SW_USER4 
    Info (332119):    -0.219        -1.146 SW_USER2 
Info (332146): Worst-case hold slack is -1.068
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.068        -1.068 SW_USER3 
    Info (332119):    -0.734        -5.746 SW_USER4 
    Info (332119):    -0.379        -2.274 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -0.297        -0.931 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.185         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.208         0.000 SW_USER2 
    Info (332119):     0.303         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -1.392
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.392       -11.067 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -0.727       -16.553 JTAG_NEXUS_TCK 
    Info (332119):    -0.314        -4.305 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info (332146): Worst-case removal slack is -0.133
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.133        -0.133 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.267         0.000 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.941         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.000      -267.084 JTAG_NEXUS_TCK 
    Info (332119):    -3.000       -35.747 CLK_BRD 
    Info (332119):    -3.000       -12.873 SW_USER3 
    Info (332119):    -3.000       -12.041 SW_USER4 
    Info (332119):    -3.000       -11.640 SW_USER2 
    Info (332119):    -1.000      -151.000 ClkDiv500:U902|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
    Info (332119):    -1.000       -16.000 ClkDiv:U901|Epson__AltSyn_AltiumAlteraDffAsync:INST_CLKOUT|lpm_ff:ff1|dffs[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 320 megabytes
    Info: Processing ended: Mon Oct 15 23:33:16 2012
    Info: Elapsed time: 00:00:21
    Info: Total CPU time (on all processors): 00:00:08


