-- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 7.2 Build 151 09/26/2007 SJ Web Edition"
 -- DATE "09/10/2008 21:54:20"

Conversion results for clock1
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |clk50                | clk[50]              |
| |dig1                 | dig[1]               |
| |dig2                 | dig[2]               |
| |dig3                 | dig[3]               |
| |dig4                 | dig[4]               |
| |dig5                 | dig[5]               |
| |dig6                 | dig[6]               |
| |led1                 | led[1]               |
| |led2                 | led[2]               |
| |led3                 | led[3]               |
| |led4                 | led[4]               |
| |t1                   | t[1]                 |
| |t2                   | t[2]                 |
| |t3                   | t[3]                 |
| |t4                   | t[4]                 |
+-----------------------+----------------------+