| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| nios_reset_clk_0_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_regs |
41 |
13 |
6 |
13 |
44 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_rx|the_uart_9600_rx_stimulus_source |
18 |
0 |
17 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_rx |
20 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_tx |
28 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600 |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600_s1 |
72 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_sysid |
3 |
17 |
1 |
17 |
32 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| the_sysid_control_slave |
53 |
1 |
2 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_spi_touch |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_spi_touch_spi_control_port |
73 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_spi_lcd22 |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_spi_lcd22_spi_control_port |
73 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_rom|the_altsyncram|auto_generated |
51 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_rom |
54 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_rom_s1 |
110 |
1 |
4 |
1 |
95 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_ram|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_ram |
54 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_ram_s1 |
109 |
1 |
4 |
1 |
95 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pd |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pd_s1 |
86 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pc |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pc_s1 |
86 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pb |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pb_s1 |
86 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pa |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pa_s1 |
86 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_cpu |
150 |
0 |
29 |
0 |
107 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_instruction_master |
131 |
0 |
2 |
0 |
52 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_data_master |
385 |
29 |
30 |
29 |
82 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_jtag_debug_module |
111 |
1 |
4 |
1 |
92 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |