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clk_0

clock_source v11.0

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cpu

altera_nios2 v11.0

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave rom.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 7 instSlaveMapParam <address-map><slave name='ram.s1' start='0x8000' end='0xE710' /><slave name='rom.s1' start='0x14000' end='0x16A10' /><slave name='cpu.jtag_debug_module' start='0x18800' end='0x19000' /></address-map> instAddrWidth 17 impl Fast icache_size _2048 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave ram.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 deviceFamilyName Cyclone III debug_triggerArming true debug_level Level2 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _0 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false dataSlaveMapParam <address-map><slave name='ram.s1' start='0x8000' end='0xE710' /><slave name='rom.s1' start='0x14000' end='0x16A10' /><slave name='cpu.jtag_debug_module' start='0x18800' end='0x19000' /><slave name='spi_touch.spi_control_port' start='0x19000' end='0x19020' /><slave name='spi_lcd22.spi_control_port' start='0x19020' end='0x19040' /><slave name='uart_9600.s1' start='0x19040' end='0x19060' /><slave name='pa.s1' start='0x19060' end='0x19070' /><slave name='pb.s1' start='0x19070' end='0x19080' /><slave name='pc.s1' start='0x19080' end='0x19090' /><slave name='pd.s1' start='0x19090' end='0x190A0' /><slave name='sysid.control_slave' start='0x190A0' end='0x190A8' /></address-map> dataAddrWidth 17 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 50000000 breakSlave cpu.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 2048 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x8020 RESET_ADDR 0x14000 BREAK_ADDR 0x18820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 17 DATA_ADDR_WIDTH 17 NUM_OF_SHADOW_REG_SETS 0

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sysid

altera_avalon_sysid v11.0

Parameters id 0 timestamp 1336205518 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 0u TIMESTAMP 1336205518u

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pa

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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rom

altera_avalon_onchip_memory2 v11.0

Parameters allowInSystemMemoryContentEditor false autoInitializationFileName rom blockType AUTO dataWidth 32 deviceFamily Cyclone III dualPort false initMemContent true initializationFileName rom instanceID NONE memorySize 10768 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable false generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "rom" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 0 DUAL_PORT 0 SINGLE_CLOCK_OP 0 SIZE_VALUE 10768u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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ram

altera_avalon_onchip_memory2 v11.0

Parameters allowInSystemMemoryContentEditor false autoInitializationFileName ram blockType AUTO dataWidth 32 deviceFamily Cyclone III dualPort false initMemContent true initializationFileName ram instanceID NONE memorySize 26384 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "ram" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 0 SINGLE_CLOCK_OP 0 SIZE_VALUE 26384u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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pb

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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pc

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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pd

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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spi_touch

altera_avalon_spi v11.0

Parameters actualClockRate 396825.0 actualSlaveSelectToSClkDelay 0.0 clockPhase 0 clockPolarity 0 dataWidth 8 disableAvalonFlowControl false inputClockRate 50000000 insertDelayBetweenSlaveSelectAndSClk false insertSync false lsbOrderedFirst false masterSPI true numberOfSlaves 1 syncRegDepth 2 targetClockRate 400000 targetSlaveSelectToSClkDelay 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DATABITS 8 DATAWIDTH 16 TARGETCLOCK 400000u CLOCKUNITS "Hz" CLOCKMULT 1 NUMSLAVES 1 ISMASTER 1 CLOCKPOLARITY 0 CLOCKPHASE 0 LSBFIRST 0 EXTRADELAY 0 INSERT_SYNC 0 SYNC_REG_DEPTH 2 TARGETSSDELAY "0.0" DELAYUNITS "ns" DELAYMULT "1.0E-9" PREFIX "spi_"

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spi_lcd22

altera_avalon_spi v11.0

Parameters actualClockRate 3571428.0 actualSlaveSelectToSClkDelay 0.0 clockPhase 0 clockPolarity 0 dataWidth 8 disableAvalonFlowControl false inputClockRate 50000000 insertDelayBetweenSlaveSelectAndSClk false insertSync false lsbOrderedFirst false masterSPI true numberOfSlaves 1 syncRegDepth 2 targetClockRate 4000000 targetSlaveSelectToSClkDelay 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DATABITS 8 DATAWIDTH 16 TARGETCLOCK 4000000u CLOCKUNITS "Hz" CLOCKMULT 1 NUMSLAVES 1 ISMASTER 1 CLOCKPOLARITY 0 CLOCKPHASE 0 LSBFIRST 0 EXTRADELAY 0 INSERT_SYNC 0 SYNC_REG_DEPTH 2 TARGETSSDELAY "0.0" DELAYUNITS "ns" DELAYMULT "1.0E-9" PREFIX "spi_"

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uart_9600

altera_avalon_uart v11.0

Parameters baud 9600 baudError 0.01 clockRate 50000000 dataBits 8 fixedBaud true parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 9600 DATA_BITS 8 FIXED_BAUD 1 PARITY 'N' STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0 SIM_TRUE_BAUD 0 SIM_CHAR_STREAM "" FREQ 50000000u