Fitter report for nios
Fri May 04 13:05:18 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Fitter Netlist Optimizations
  7. Ignored Assignments
  8. Incremental Compilation Preservation Summary
  9. Incremental Compilation Partition Settings
 10. Incremental Compilation Placement Preservation
 11. Pin-Out File
 12. Fitter Resource Usage Summary
 13. Fitter Partition Statistics
 14. Input Pins
 15. Output Pins
 16. Bidir Pins
 17. Dual Purpose and Dedicated Pins
 18. I/O Bank Usage
 19. All Package Pins
 20. PLL Summary
 21. PLL Usage
 22. Output Pin Default Load For Reported TCO
 23. Fitter Resource Utilization by Entity
 24. Delay Chain Summary
 25. Pad To Core Delay Chain Fanout
 26. Control Signals
 27. Global & Other Fast Signals
 28. Non-Global High Fan-Out Signals
 29. Fitter RAM Summary
 30. |nios|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_i851:auto_generated|ALTSYNCRAM
 31. Fitter DSP Block Usage Summary
 32. DSP Block Details
 33. Interconnect Usage Summary
 34. LAB Logic Elements
 35. LAB-wide Signals
 36. LAB Signals Sourced
 37. LAB Signals Sourced Out
 38. LAB Distinct Inputs
 39. I/O Rules Summary
 40. I/O Rules Details
 41. I/O Rules Matrix
 42. Fitter Device Options
 43. Operating Settings and Conditions
 44. Fitter Messages
 45. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Fitter Summary                                                                 ;
+------------------------------------+-------------------------------------------+
; Fitter Status                      ; Successful - Fri May 04 13:05:18 2012     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; nios                                      ;
; Top-level Entity Name              ; nios                                      ;
; Family                             ; Cyclone III                               ;
; Device                             ; EP3C16Q240C8                              ;
; Timing Models                      ; Final                                     ;
; Total logic elements               ; 4,354 / 15,408 ( 28 % )                   ;
;     Total combinational functions  ; 3,766 / 15,408 ( 24 % )                   ;
;     Dedicated logic registers      ; 2,804 / 15,408 ( 18 % )                   ;
; Total registers                    ; 2873                                      ;
; Total pins                         ; 102 / 161 ( 63 % )                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 55,680 / 516,096 ( 11 % )                 ;
; Embedded Multiplier 9-bit elements ; 4 / 112 ( 4 % )                           ;
; Total PLLs                         ; 1 / 4 ( 25 % )                            ;
+------------------------------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                          ;
+----------------------------------------------------------------------------+---------------------+---------------------------------------+
; Option                                                                     ; Setting             ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------+---------------------------------------+
; Device                                                                     ; EP3C16Q240C8        ;                                       ;
; Minimum Core Junction Temperature                                          ; 0                   ;                                       ;
; Maximum Core Junction Temperature                                          ; 85                  ;                                       ;
; Fit Attempts to Skip                                                       ; 0                   ; 0.0                                   ;
; Device I/O Standard                                                        ; 3.3-V LVTTL         ;                                       ;
; Reserve all unused pins                                                    ; As input tri-stated ; As input tri-stated with weak pull-up ;
; Use smart compilation                                                      ; Off                 ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                  ; On                                    ;
; Enable compact report table                                                ; Off                 ; Off                                   ;
; Use TimeQuest Timing Analyzer                                              ; On                  ; On                                    ;
; Auto Merge PLLs                                                            ; On                  ; On                                    ;
; Router Timing Optimization Level                                           ; Normal              ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                 ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                 ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                 ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths           ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; Off                 ; Off                                   ;
; PowerPlay Power Optimization                                               ; Normal compilation  ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                 ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation  ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                 ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                 ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal              ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                 ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically       ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically       ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                   ; 1                                     ;
; PCI I/O                                                                    ; Off                 ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                 ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                 ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                ; Auto                                  ;
; Auto Delay Chains                                                          ; On                  ; On                                    ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                 ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                 ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                 ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                 ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                 ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                 ; Off                                   ;
; Perform Register Retiming for Performance                                  ; Off                 ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                 ; Off                                   ;
; Fitter Effort                                                              ; Auto Fit            ; Auto Fit                              ;
; Physical Synthesis Effort Level                                            ; Normal              ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                ; Auto                                  ;
; Auto Global Clock                                                          ; On                  ; On                                    ;
; Auto Global Register Control Signals                                       ; On                  ; On                                    ;
; Synchronizer Identification                                                ; Off                 ; Off                                   ;
; Enable Beneficial Skew Optimization                                        ; On                  ; On                                    ;
; Optimize Design for Metastability                                          ; On                  ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                 ; Off                                   ;
; RAM Bit Reservation (Cyclone III)                                          ; Off                 ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                 ; Off                                   ;
+----------------------------------------------------------------------------+---------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.31        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;  18.2%      ;
+----------------------------+-------------+


+----------------------------------------------------------------+
; I/O Assignment Warnings                                        ;
+---------------------------------------+------------------------+
; Pin Name                              ; Reason                 ;
+---------------------------------------+------------------------+
; altpll_0_c0_out                       ; Missing drive strength ;
; altpll_0_c1_out                       ; Missing drive strength ;
; locked_from_the_altpll_0              ; Missing drive strength ;
; phasedone_from_the_altpll_0           ; Missing drive strength ;
; dclk_from_the_epcs_flash_controller_0 ; Missing drive strength ;
; sce_from_the_epcs_flash_controller_0  ; Missing drive strength ;
; sdo_from_the_epcs_flash_controller_0  ; Missing drive strength ;
; out_port_from_the_lcd_cs              ; Missing drive strength ;
; out_port_from_the_lcd_rs              ; Missing drive strength ;
; out_port_from_the_lcd_wr              ; Missing drive strength ;
; out_port_from_the_reset               ; Missing drive strength ;
; out_port_from_the_sd_cs               ; Missing drive strength ;
; zs_addr_from_the_sdram_0[0]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[1]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[2]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[3]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[4]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[5]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[6]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[7]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[8]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[9]           ; Missing drive strength ;
; zs_addr_from_the_sdram_0[10]          ; Missing drive strength ;
; zs_addr_from_the_sdram_0[11]          ; Missing drive strength ;
; zs_addr_from_the_sdram_0[12]          ; Missing drive strength ;
; zs_ba_from_the_sdram_0[0]             ; Missing drive strength ;
; zs_ba_from_the_sdram_0[1]             ; Missing drive strength ;
; zs_cas_n_from_the_sdram_0             ; Missing drive strength ;
; zs_cke_from_the_sdram_0               ; Missing drive strength ;
; zs_cs_n_from_the_sdram_0              ; Missing drive strength ;
; zs_dqm_from_the_sdram_0[0]            ; Missing drive strength ;
; zs_dqm_from_the_sdram_0[1]            ; Missing drive strength ;
; zs_ras_n_from_the_sdram_0             ; Missing drive strength ;
; zs_we_n_from_the_sdram_0              ; Missing drive strength ;
; MOSI_from_the_spi_lcd22               ; Missing drive strength ;
; SCLK_from_the_spi_lcd22               ; Missing drive strength ;
; SS_n_from_the_spi_lcd22               ; Missing drive strength ;
; MOSI_from_the_spi_sdcard              ; Missing drive strength ;
; SCLK_from_the_spi_sdcard              ; Missing drive strength ;
; SS_n_from_the_spi_sdcard              ; Missing drive strength ;
; MOSI_from_the_spi_touch               ; Missing drive strength ;
; SCLK_from_the_spi_touch               ; Missing drive strength ;
; SS_n_from_the_spi_touch               ; Missing drive strength ;
; out_port_from_the_touch_cs            ; Missing drive strength ;
; txd_from_the_uart_9600                ; Missing drive strength ;
; bidir_port_to_and_from_the_DS18B20    ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[0]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[1]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[2]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[3]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[4]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[5]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[6]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pa[7]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[0]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[1]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[2]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[3]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[4]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[5]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[6]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pb[7]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[0]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[1]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[2]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[3]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[4]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[5]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[6]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pc[7]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[0]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[1]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[2]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[3]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[4]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[5]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[6]      ; Missing drive strength ;
; bidir_port_to_and_from_the_pd[7]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[0]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[1]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[2]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[3]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[4]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[5]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[6]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[7]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[8]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[9]      ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[10]     ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[11]     ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[12]     ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[13]     ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[14]     ; Missing drive strength ;
; zs_dq_to_and_from_the_sdram_0[15]     ; Missing drive strength ;
+---------------------------------------+------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node                                                                                 ; Action          ; Operation        ; Reason                                 ; Node Port ; Node Port Name ; Destination Node                                                                                                                                                                             ; Destination Port ; Destination Port Name ;
+--------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; cpu:the_cpu|A_mul_src1[0]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[0]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[0]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[1]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[1]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[1]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[2]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[2]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[2]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[3]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[3]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[3]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[4]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[4]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[4]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[5]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[5]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[5]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[6]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[6]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[6]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[7]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[7]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[7]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[8]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[8]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[8]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[9]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[9]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[9]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[10]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[10]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[10]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[11]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[11]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[11]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[12]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[12]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[12]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[13]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[13]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[13]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[14]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[14]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[14]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[15]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[15]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src1[15]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src1[16]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[17]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[18]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[19]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[20]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[21]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[22]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[23]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[24]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[25]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[26]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[27]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[28]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[29]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[30]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src1[31]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAA            ;                       ;
; cpu:the_cpu|A_mul_src2[0]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[0]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[0]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[0]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[1]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[1]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[1]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[1]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[2]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[2]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[2]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[2]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[3]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[3]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[3]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[3]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[4]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[4]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[4]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[4]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[5]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[5]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[5]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[5]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[6]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[6]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[6]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[6]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[7]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[7]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[7]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[7]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[8]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[8]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[8]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[8]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[9]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[9]                                                            ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[9]~_Duplicate_1                                                                                                                                                       ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[9]~_Duplicate_1                                               ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[10]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[10]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[10]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[10]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[11]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[11]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[11]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[11]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[12]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[12]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[12]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[12]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[13]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[13]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[13]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[13]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[14]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[14]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[14]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[14]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[15]                                                           ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|A_mul_src2[15]                                                           ; Duplicated      ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|A_mul_src2[15]~_Duplicate_1                                                                                                                                                      ; Q                ;                       ;
; cpu:the_cpu|A_mul_src2[15]~_Duplicate_1                                              ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2                                                ; DATAB            ;                       ;
; cpu:the_cpu|D_bht_data[0]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_2of1:auto_generated|q_b[0]                                                                                           ; PORTBDATAOUT     ;                       ;
; cpu:the_cpu|D_bht_data[1]                                                            ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_2of1:auto_generated|q_b[1]                                                                                           ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[0] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[0] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[1] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[1] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[2] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[2] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[3] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[3] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[4] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[4] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[5] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[5] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[6] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[6] ; PORTBDATAOUT     ;                       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[7] ; Packed Register ; Register Packing ; Timing optimization                    ; Q         ;                ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|q_b[7] ; PORTBDATAOUT     ;                       ;
; sdram_0:the_sdram_0|m_addr[0]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[0]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[1]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[1]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[2]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[2]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[3]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[3]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[4]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[4]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[5]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[5]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[6]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[6]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[7]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[7]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[8]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[8]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[9]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[9]~output                                                                                                                                                           ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[10]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[10]~output                                                                                                                                                          ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[11]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[11]~output                                                                                                                                                          ; I                ;                       ;
; sdram_0:the_sdram_0|m_addr[12]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_addr_from_the_sdram_0[12]~output                                                                                                                                                          ; I                ;                       ;
; sdram_0:the_sdram_0|m_bank[0]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_ba_from_the_sdram_0[0]~output                                                                                                                                                             ; I                ;                       ;
; sdram_0:the_sdram_0|m_bank[1]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_ba_from_the_sdram_0[1]~output                                                                                                                                                             ; I                ;                       ;
; sdram_0:the_sdram_0|m_cmd[0]                                                         ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_cmd[0]~_Duplicate_1                                                                                                                                                    ; Q                ;                       ;
; sdram_0:the_sdram_0|m_cmd[0]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_we_n_from_the_sdram_0~output                                                                                                                                                              ; I                ;                       ;
; sdram_0:the_sdram_0|m_cmd[0]                                                         ; Inverted        ; Register Packing ; Fast Output Register assignment        ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|m_cmd[1]                                                         ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_cmd[1]~_Duplicate_1                                                                                                                                                    ; Q                ;                       ;
; sdram_0:the_sdram_0|m_cmd[1]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_cas_n_from_the_sdram_0~output                                                                                                                                                             ; I                ;                       ;
; sdram_0:the_sdram_0|m_cmd[1]                                                         ; Inverted        ; Register Packing ; Fast Output Register assignment        ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|m_cmd[2]                                                         ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_cmd[2]~_Duplicate_1                                                                                                                                                    ; Q                ;                       ;
; sdram_0:the_sdram_0|m_cmd[2]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_ras_n_from_the_sdram_0~output                                                                                                                                                             ; I                ;                       ;
; sdram_0:the_sdram_0|m_cmd[2]                                                         ; Inverted        ; Register Packing ; Fast Output Register assignment        ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|m_cmd[3]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_cs_n_from_the_sdram_0~output                                                                                                                                                              ; I                ;                       ;
; sdram_0:the_sdram_0|m_cmd[3]                                                         ; Inverted        ; Register Packing ; Fast Output Register assignment        ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|m_data[0]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[0]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[0]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[0]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[1]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[1]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[1]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[1]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[2]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[2]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[2]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[2]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[3]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[3]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[3]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[3]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[4]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[4]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[4]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[4]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[5]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[5]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[5]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[5]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[6]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[6]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[6]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[6]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[7]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[7]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[7]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[7]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[8]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[8]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[8]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[8]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[9]                                                        ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[9]~_Duplicate_1                                                                                                                                                   ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[9]                                                        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[9]~output                                                                                                                                                      ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[10]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[10]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[10]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[10]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[11]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[11]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[11]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[11]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[12]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[12]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[12]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[12]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[13]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[13]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[13]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[13]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[14]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[14]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[14]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[14]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_data[15]                                                       ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; sdram_0:the_sdram_0|m_data[15]~_Duplicate_1                                                                                                                                                  ; Q                ;                       ;
; sdram_0:the_sdram_0|m_data[15]                                                       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[15]~output                                                                                                                                                     ; I                ;                       ;
; sdram_0:the_sdram_0|m_dqm[0]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dqm_from_the_sdram_0[0]~output                                                                                                                                                            ; I                ;                       ;
; sdram_0:the_sdram_0|m_dqm[1]                                                         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; Q         ;                ; zs_dqm_from_the_sdram_0[1]~output                                                                                                                                                            ; I                ;                       ;
; sdram_0:the_sdram_0|oe                                                               ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_1                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe                                                               ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[0]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe                                                               ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_1                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_2                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_1                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[1]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_1                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_2                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_3                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_2                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[2]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_2                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_3                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_4                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_3                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[3]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_3                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_4                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_5                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_4                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[4]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_4                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_5                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_6                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_5                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[5]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_5                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_6                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_7                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_6                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[6]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_6                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_7                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_8                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_7                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[7]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_7                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_8                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_9                                                                                                                                                          ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_8                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[8]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_8                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_9                                                  ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_10                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_9                                                  ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[9]~output                                                                                                                                                      ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_9                                                  ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_10                                                 ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_11                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_10                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[10]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_10                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_11                                                 ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_12                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_11                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[11]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_11                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_12                                                 ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_13                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_12                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[12]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_12                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_13                                                 ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_14                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_13                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[13]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_13                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_14                                                 ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; sdram_0:the_sdram_0|oe~_Duplicate_15                                                                                                                                                         ; Q                ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_14                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[14]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_14                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_15                                                 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[15]~output                                                                                                                                                     ; OE               ;                       ;
; sdram_0:the_sdram_0|oe~_Duplicate_15                                                 ; Inverted        ; Register Packing ; Fast Output Enable Register assignment ; Q         ;                ;                                                                                                                                                                                              ;                  ;                       ;
; sdram_0:the_sdram_0|za_data[0]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[0]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[1]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[1]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[2]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[2]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[3]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[3]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[4]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[4]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[5]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[5]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[6]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[6]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[7]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[7]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[8]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[8]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[9]                                                       ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[9]~input                                                                                                                                                       ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[10]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[10]~input                                                                                                                                                      ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[11]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[11]~input                                                                                                                                                      ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[12]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[12]~input                                                                                                                                                      ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[13]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[13]~input                                                                                                                                                      ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[14]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[14]~input                                                                                                                                                      ; O                ;                       ;
; sdram_0:the_sdram_0|za_data[15]                                                      ; Packed Register ; Register Packing ; Fast Input Register assignment         ; Q         ;                ; zs_dq_to_and_from_the_sdram_0[15]~input                                                                                                                                                      ; O                ;                       ;
+--------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                                                   ;
+-----------------------------+----------------+--------------+------------+---------------+----------------------------+
; Name                        ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source             ;
+-----------------------------+----------------+--------------+------------+---------------+----------------------------+
; Fast Output Enable Register ; sdram_0        ;              ; m_data[0]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[10] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[11] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[12] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[13] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[14] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[15] ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[1]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[2]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[3]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[4]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[5]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[6]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[7]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[8]  ; ON            ; Compiler or HDL Assignment ;
; Fast Output Enable Register ; sdram_0        ;              ; m_data[9]  ; ON            ; Compiler or HDL Assignment ;
+-----------------------------+----------------+--------------+------------+---------------+----------------------------+


+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+---------------------+------------------------+
; Type                ; Value                  ;
+---------------------+------------------------+
; Placement (by node) ;                        ;
;     -- Requested    ; 0 / 7117 ( 0.00 % )    ;
;     -- Achieved     ; 0 / 7117 ( 0.00 % )    ;
;                     ;                        ;
; Routing (by net)    ;                        ;
;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
+---------------------+------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_hub:auto_hub               ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                             ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Top                            ; 6916    ; 0                 ; N/A                     ; Source File       ;
; sld_hub:auto_hub               ; 198     ; 0                 ; N/A                     ; Post-Synthesis    ;
; hard_block:auto_generated_inst ; 3       ; 0                 ; N/A                     ; Source File       ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Program/EP3C16/nios/LCD22+epcs16+sdram+bigpicture/nios.pin.


+-----------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                         ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                   ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Total logic elements                        ; 4,354 / 15,408 ( 28 % )                                                 ;
;     -- Combinational with no register       ; 1550                                                                    ;
;     -- Register only                        ; 588                                                                     ;
;     -- Combinational with a register        ; 2216                                                                    ;
;                                             ;                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                         ;
;     -- 4 input functions                    ; 2072                                                                    ;
;     -- 3 input functions                    ; 1195                                                                    ;
;     -- <=2 input functions                  ; 499                                                                     ;
;     -- Register only                        ; 588                                                                     ;
;                                             ;                                                                         ;
; Logic elements by mode                      ;                                                                         ;
;     -- normal mode                          ; 3466                                                                    ;
;     -- arithmetic mode                      ; 300                                                                     ;
;                                             ;                                                                         ;
; Total registers*                            ; 2,873 / 16,138 ( 18 % )                                                 ;
;     -- Dedicated logic registers            ; 2,804 / 15,408 ( 18 % )                                                 ;
;     -- I/O registers                        ; 69 / 730 ( 9 % )                                                        ;
;                                             ;                                                                         ;
; Total LABs:  partially or completely used   ; 339 / 963 ( 35 % )                                                      ;
; User inserted logic elements                ; 0                                                                       ;
; Virtual pins                                ; 0                                                                       ;
; I/O pins                                    ; 102 / 161 ( 63 % )                                                      ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )                                                          ;
;     -- Dedicated input pins                 ; 3 / 9 ( 33 % )                                                          ;
; Global signals                              ; 8                                                                       ;
; M9Ks                                        ; 13 / 56 ( 23 % )                                                        ;
; Total block memory bits                     ; 55,680 / 516,096 ( 11 % )                                               ;
; Total block memory implementation bits      ; 119,808 / 516,096 ( 23 % )                                              ;
; Embedded Multiplier 9-bit elements          ; 4 / 112 ( 4 % )                                                         ;
; PLLs                                        ; 1 / 4 ( 25 % )                                                          ;
; Global clocks                               ; 8 / 20 ( 40 % )                                                         ;
; JTAGs                                       ; 1 / 1 ( 100 % )                                                         ;
; CRC blocks                                  ; 0 / 1 ( 0 % )                                                           ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )                                                           ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )                                                           ;
; Average interconnect usage (total/H/V)      ; 15% / 15% / 15%                                                         ;
; Peak interconnect usage (total/H/V)         ; 57% / 57% / 58%                                                         ;
; Maximum fan-out node                        ; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0]~clkctrl ;
; Maximum fan-out                             ; 2713                                                                    ;
; Highest non-global fan-out signal           ; cpu:the_cpu|A_stall~0                                                   ;
; Highest non-global fan-out                  ; 656                                                                     ;
; Total fan-out                               ; 24647                                                                   ;
; Average fan-out                             ; 3.37                                                                    ;
+---------------------------------------------+-------------------------------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                   ;
+----------------------------------------------+-----------------------+-----------------------+--------------------------------+
; Statistic                                    ; Top                   ; sld_hub:auto_hub      ; hard_block:auto_generated_inst ;
+----------------------------------------------+-----------------------+-----------------------+--------------------------------+
; Difficulty Clustering Region                 ; Low                   ; Low                   ; Low                            ;
;                                              ;                       ;                       ;                                ;
; Total logic elements                         ; 4224 / 15408 ( 27 % ) ; 130 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
;     -- Combinational with no register        ; 1496                  ; 54                    ; 0                              ;
;     -- Register only                         ; 580                   ; 8                     ; 0                              ;
;     -- Combinational with a register         ; 2148                  ; 68                    ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Logic element usage by number of LUT inputs  ;                       ;                       ;                                ;
;     -- 4 input functions                     ; 2021                  ; 51                    ; 0                              ;
;     -- 3 input functions                     ; 1149                  ; 46                    ; 0                              ;
;     -- <=2 input functions                   ; 474                   ; 25                    ; 0                              ;
;     -- Register only                         ; 580                   ; 8                     ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Logic elements by mode                       ;                       ;                       ;                                ;
;     -- normal mode                           ; 3348                  ; 118                   ; 0                              ;
;     -- arithmetic mode                       ; 296                   ; 4                     ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Total registers                              ; 2797                  ; 76                    ; 0                              ;
;     -- Dedicated logic registers             ; 2728 / 15408 ( 17 % ) ; 76 / 15408 ( < 1 % )  ; 0 / 15408 ( 0 % )              ;
;     -- I/O registers                         ; 138                   ; 0                     ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Total LABs:  partially or completely used    ; 327 / 963 ( 33 % )    ; 12 / 963 ( 1 % )      ; 0 / 963 ( 0 % )                ;
;                                              ;                       ;                       ;                                ;
; Virtual pins                                 ; 0                     ; 0                     ; 0                              ;
; I/O pins                                     ; 102                   ; 0                     ; 0                              ;
; Embedded Multiplier 9-bit elements           ; 4 / 112 ( 3 % )       ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
; Total memory bits                            ; 55680                 ; 0                     ; 0                              ;
; Total RAM block bits                         ; 119808                ; 0                     ; 0                              ;
; JTAG                                         ; 1 / 1 ( 100 % )       ; 0 / 1 ( 0 % )         ; 0 / 1 ( 0 % )                  ;
; PLL                                          ; 0 / 4 ( 0 % )         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
; M9K                                          ; 13 / 56 ( 23 % )      ; 0 / 56 ( 0 % )        ; 0 / 56 ( 0 % )                 ;
; Clock control block                          ; 6 / 24 ( 25 % )       ; 0 / 24 ( 0 % )        ; 2 / 24 ( 8 % )                 ;
; Double Data Rate I/O output circuitry        ; 37 / 336 ( 11 % )     ; 0 / 336 ( 0 % )       ; 0 / 336 ( 0 % )                ;
; Double Data Rate I/O output enable circuitry ; 16 / 336 ( 4 % )      ; 0 / 336 ( 0 % )       ; 0 / 336 ( 0 % )                ;
;                                              ;                       ;                       ;                                ;
; Connections                                  ;                       ;                       ;                                ;
;     -- Input Connections                     ; 3026                  ; 117                   ; 2                              ;
;     -- Registered Input Connections          ; 2822                  ; 84                    ; 0                              ;
;     -- Output Connections                    ; 260                   ; 169                   ; 2716                           ;
;     -- Registered Output Connections         ; 4                     ; 168                   ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Internal Connections                         ;                       ;                       ;                                ;
;     -- Total Connections                     ; 24232                 ; 826                   ; 2721                           ;
;     -- Registered Connections                ; 11468                 ; 591                   ; 0                              ;
;                                              ;                       ;                       ;                                ;
; External Connections                         ;                       ;                       ;                                ;
;     -- Top                                   ; 284                   ; 284                   ; 2718                           ;
;     -- sld_hub:auto_hub                      ; 284                   ; 2                     ; 0                              ;
;     -- hard_block:auto_generated_inst        ; 2718                  ; 0                     ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Partition Interface                          ;                       ;                       ;                                ;
;     -- Input Ports                           ; 48                    ; 22                    ; 2                              ;
;     -- Output Ports                          ; 52                    ; 39                    ; 3                              ;
;     -- Bidir Ports                           ; 49                    ; 0                     ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Registered Ports                             ;                       ;                       ;                                ;
;     -- Registered Input Ports                ; 0                     ; 3                     ; 0                              ;
;     -- Registered Output Ports               ; 0                     ; 29                    ; 0                              ;
;                                              ;                       ;                       ;                                ;
; Port Connectivity                            ;                       ;                       ;                                ;
;     -- Input Ports driven by GND             ; 0                     ; 9                     ; 0                              ;
;     -- Output Ports driven by GND            ; 0                     ; 0                     ; 0                              ;
;     -- Input Ports driven by VCC             ; 0                     ; 0                     ; 0                              ;
;     -- Output Ports driven by VCC            ; 0                     ; 0                     ; 0                              ;
;     -- Input Ports with no Source            ; 0                     ; 0                     ; 0                              ;
;     -- Output Ports with no Source           ; 0                     ; 0                     ; 0                              ;
;     -- Input Ports with no Fanout            ; 0                     ; 1                     ; 0                              ;
;     -- Output Ports with no Fanout           ; 0                     ; 25                    ; 0                              ;
+----------------------------------------------+-----------------------+-----------------------+--------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                                                ;
+--------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name                                 ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+--------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; MISO_to_the_spi_lcd22                ; 78    ; 3        ; 14           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; On           ; 3.3-V LVTTL  ; --                        ; User                 ;
; MISO_to_the_spi_sdcard               ; 224   ; 8        ; 9            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; On           ; 3.3-V LVTTL  ; --                        ; Fitter               ;
; MISO_to_the_spi_touch                ; 70    ; 3        ; 7            ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; On           ; 3.3-V LVTTL  ; --                        ; Fitter               ;
; clk_ex                               ; 31    ; 1        ; 0            ; 14           ; 0            ; 25                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; data0_to_the_epcs_flash_controller_0 ; 24    ; 1        ; 0            ; 20           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; On           ; 3.3-V LVTTL  ; --                        ; User                 ;
; in_port_to_the_touch_irq             ; 63    ; 3        ; 3            ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; On           ; 3.3-V LVTTL  ; --                        ; User                 ;
; reset_n                              ; 6     ; 1        ; 0            ; 27           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; rxd_to_the_uart_9600                 ; 109   ; 4        ; 30           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; Fitter               ;
+--------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+---------------------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
; Name                                  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------------------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
; MOSI_from_the_spi_lcd22               ; 83    ; 3        ; 16           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; MOSI_from_the_spi_sdcard              ; 202   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; MOSI_from_the_spi_touch               ; 223   ; 8        ; 11           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; SCLK_from_the_spi_lcd22               ; 88    ; 3        ; 19           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; SCLK_from_the_spi_sdcard              ; 196   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; SCLK_from_the_spi_touch               ; 174   ; 6        ; 41           ; 25           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; SS_n_from_the_spi_lcd22               ; 220   ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; SS_n_from_the_spi_sdcard              ; 203   ; 7        ; 23           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; SS_n_from_the_spi_touch               ; 230   ; 8        ; 7            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; altpll_0_c0_out                       ; 183   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; altpll_0_c1_out                       ; 145   ; 5        ; 41           ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; dclk_from_the_epcs_flash_controller_0 ; 23    ; 1        ; 0            ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; locked_from_the_altpll_0              ; 100   ; 4        ; 26           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; out_port_from_the_lcd_cs              ; 94    ; 4        ; 23           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; out_port_from_the_lcd_rs              ; 99    ; 4        ; 26           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; out_port_from_the_lcd_wr              ; 189   ; 7        ; 32           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; out_port_from_the_reset               ; 81    ; 3        ; 16           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; out_port_from_the_sd_cs               ; 194   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; out_port_from_the_touch_cs            ; 69    ; 3        ; 5            ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; phasedone_from_the_altpll_0           ; 73    ; 3        ; 7            ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; sce_from_the_epcs_flash_controller_0  ; 14    ; 1        ; 0            ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; sdo_from_the_epcs_flash_controller_0  ; 12    ; 1        ; 0            ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; txd_from_the_uart_9600                ; 93    ; 4        ; 23           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[0]           ; 55    ; 2        ; 0            ; 4            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[10]          ; 50    ; 2        ; 0            ; 5            ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[11]          ; 142   ; 5        ; 41           ; 12           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[12]          ; 143   ; 5        ; 41           ; 13           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[1]           ; 52    ; 2        ; 0            ; 4            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[2]           ; 57    ; 2        ; 0            ; 3            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[3]           ; 56    ; 2        ; 0            ; 3            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[4]           ; 131   ; 5        ; 41           ; 5            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[5]           ; 132   ; 5        ; 41           ; 5            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[6]           ; 134   ; 5        ; 41           ; 8            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[7]           ; 135   ; 5        ; 41           ; 9            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[8]           ; 137   ; 5        ; 41           ; 9            ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_addr_from_the_sdram_0[9]           ; 139   ; 5        ; 41           ; 10           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_ba_from_the_sdram_0[0]             ; 46    ; 2        ; 0            ; 6            ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_ba_from_the_sdram_0[1]             ; 51    ; 2        ; 0            ; 5            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_cas_n_from_the_sdram_0             ; 45    ; 2        ; 0            ; 9            ; 0            ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_cke_from_the_sdram_0               ; 144   ; 5        ; 41           ; 13           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_cs_n_from_the_sdram_0              ; 49    ; 2        ; 0            ; 5            ; 7            ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_dqm_from_the_sdram_0[0]            ; 41    ; 2        ; 0            ; 10           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_dqm_from_the_sdram_0[1]            ; 146   ; 5        ; 41           ; 14           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_ras_n_from_the_sdram_0             ; 44    ; 2        ; 0            ; 10           ; 21           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
; zs_we_n_from_the_sdram_0              ; 43    ; 2        ; 0            ; 10           ; 7            ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+---------------------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-----------------------------------------+---------------------+
; Name                               ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                    ; Output Enable Group ;
+------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-----------------------------------------+---------------------+
; bidir_port_to_and_from_the_DS18B20 ; 148   ; 5        ; 41           ; 14           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; DS18B20:the_DS18B20|data_dir (inverted) ; -                   ;
; bidir_port_to_and_from_the_pa[0]   ; 187   ; 7        ; 32           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[0] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[1]   ; 147   ; 5        ; 41           ; 14           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[1] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[2]   ; 186   ; 7        ; 35           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[2] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[3]   ; 168   ; 6        ; 41           ; 23           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[3] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[4]   ; 101   ; 4        ; 26           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[4] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[5]   ; 188   ; 7        ; 32           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[5] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[6]   ; 85    ; 3        ; 19           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[6] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pa[7]   ; 106   ; 4        ; 30           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pa:the_pa|data_dir[7] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[0]   ; 198   ; 7        ; 28           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[0] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[1]   ; 98    ; 4        ; 26           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[1] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[2]   ; 195   ; 7        ; 28           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[2] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[3]   ; 200   ; 7        ; 26           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[3] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[4]   ; 197   ; 7        ; 28           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[4] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[5]   ; 173   ; 6        ; 41           ; 24           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[5] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[6]   ; 199   ; 7        ; 26           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[6] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pb[7]   ; 201   ; 7        ; 26           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pb:the_pb|data_dir[7] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[0]   ; 82    ; 3        ; 16           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[0] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[1]   ; 87    ; 3        ; 19           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[1] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[2]   ; 76    ; 3        ; 14           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[2] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[3]   ; 222   ; 8        ; 11           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[3] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[4]   ; 218   ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[4] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[5]   ; 84    ; 3        ; 19           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[5] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[6]   ; 80    ; 3        ; 14           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[6] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pc[7]   ; 214   ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pc:the_pc|data_dir[7] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[0]   ; 95    ; 4        ; 23           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[0] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[1]   ; 86    ; 3        ; 19           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[1] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[2]   ; 219   ; 8        ; 14           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[2] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[3]   ; 217   ; 8        ; 14           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[3] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[4]   ; 216   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[4] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[5]   ; 167   ; 6        ; 41           ; 23           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[5] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[6]   ; 221   ; 8        ; 11           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[6] (inverted)        ; -                   ;
; bidir_port_to_and_from_the_pd[7]   ; 207   ; 7        ; 21           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; Fitter               ; 0 pF ; pd:the_pd|data_dir[7] (inverted)        ; -                   ;
; zs_dq_to_and_from_the_sdram_0[0]   ; 13    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe                  ; -                   ;
; zs_dq_to_and_from_the_sdram_0[10]  ; 161   ; 6        ; 41           ; 18           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_10    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[11]  ; 162   ; 6        ; 41           ; 19           ; 14           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_11    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[12]  ; 164   ; 6        ; 41           ; 19           ; 7            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_12    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[13]  ; 166   ; 6        ; 41           ; 19           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_13    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[14]  ; 169   ; 6        ; 41           ; 23           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_14    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[15]  ; 171   ; 6        ; 41           ; 24           ; 7            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_15    ; -                   ;
; zs_dq_to_and_from_the_sdram_0[1]   ; 9     ; 1        ; 0            ; 26           ; 14           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_1     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[2]   ; 18    ; 1        ; 0            ; 22           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_2     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[3]   ; 21    ; 1        ; 0            ; 21           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_3     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[4]   ; 22    ; 1        ; 0            ; 21           ; 21           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_4     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[5]   ; 37    ; 2        ; 0            ; 12           ; 21           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_5     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[6]   ; 38    ; 2        ; 0            ; 11           ; 0            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_6     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[7]   ; 39    ; 2        ; 0            ; 11           ; 7            ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_7     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[8]   ; 159   ; 6        ; 41           ; 18           ; 21           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_8     ; -                   ;
; zs_dq_to_and_from_the_sdram_0[9]   ; 160   ; 6        ; 41           ; 18           ; 14           ; 0                     ; 4                  ; no     ; yes            ; yes             ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; sdram_0:the_sdram_0|oe~_Duplicate_9     ; -                   ;
+------------------------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-----------------------------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                                                  ;
+----------+------------------------------------------+------------------------+---------------------------------------+---------------------------+
; Location ; Pin Name                                 ; Reserved As            ; User Signal Name                      ; Pin Type                  ;
+----------+------------------------------------------+------------------------+---------------------------------------+---------------------------+
; 12       ; DIFFIO_L4n, DATA1, ASDO                  ; Use as regular IO      ; sdo_from_the_epcs_flash_controller_0  ; Dual Purpose Pin          ;
; 14       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; Use as regular IO      ; sce_from_the_epcs_flash_controller_0  ; Dual Purpose Pin          ;
; 17       ; nSTATUS                                  ; -                      ; -                                     ; Dedicated Programming Pin ;
; 23       ; DCLK                                     ; Use as regular IO      ; dclk_from_the_epcs_flash_controller_0 ; Dual Purpose Pin          ;
; 24       ; DATA0                                    ; Use as regular IO      ; data0_to_the_epcs_flash_controller_0  ; Dual Purpose Pin          ;
; 25       ; nCONFIG                                  ; -                      ; -                                     ; Dedicated Programming Pin ;
; 26       ; TDI                                      ; -                      ; altera_reserved_tdi                   ; JTAG Pin                  ;
; 27       ; TCK                                      ; -                      ; altera_reserved_tck                   ; JTAG Pin                  ;
; 28       ; TMS                                      ; -                      ; altera_reserved_tms                   ; JTAG Pin                  ;
; 29       ; TDO                                      ; -                      ; altera_reserved_tdo                   ; JTAG Pin                  ;
; 30       ; nCE                                      ; -                      ; -                                     ; Dedicated Programming Pin ;
; 144      ; DIFFIO_R21n, DEV_OE                      ; Use as regular IO      ; zs_cke_from_the_sdram_0               ; Dual Purpose Pin          ;
; 145      ; DIFFIO_R21p, DEV_CLRn                    ; Use as regular IO      ; altpll_0_c1_out                       ; Dual Purpose Pin          ;
; 153      ; CONF_DONE                                ; -                      ; -                                     ; Dedicated Programming Pin ;
; 155      ; MSEL0                                    ; -                      ; -                                     ; Dedicated Programming Pin ;
; 157      ; MSEL1                                    ; -                      ; -                                     ; Dedicated Programming Pin ;
; 158      ; MSEL2                                    ; -                      ; -                                     ; Dedicated Programming Pin ;
; 158      ; MSEL3                                    ; -                      ; -                                     ; Dedicated Programming Pin ;
; 159      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO      ; zs_dq_to_and_from_the_sdram_0[8]      ; Dual Purpose Pin          ;
; 160      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO      ; zs_dq_to_and_from_the_sdram_0[9]      ; Dual Purpose Pin          ;
; 162      ; DIFFIO_R16n, nCEO                        ; Use as programming pin ; zs_dq_to_and_from_the_sdram_0[11]     ; Dual Purpose Pin          ;
; 164      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO      ; zs_dq_to_and_from_the_sdram_0[12]     ; Dual Purpose Pin          ;
; 167      ; DIFFIO_R9n, nWE                          ; Use as regular IO      ; bidir_port_to_and_from_the_pd[5]      ; Dual Purpose Pin          ;
; 168      ; DIFFIO_R9p, nOE                          ; Use as regular IO      ; bidir_port_to_and_from_the_pa[3]      ; Dual Purpose Pin          ;
; 174      ; DIFFIO_R6n, nAVD                         ; Use as regular IO      ; SCLK_from_the_spi_touch               ; Dual Purpose Pin          ;
; 194      ; DIFFIO_T25p, PADD2                       ; Use as regular IO      ; out_port_from_the_sd_cs               ; Dual Purpose Pin          ;
; 196      ; DIFFIO_T23n, PADD3                       ; Use as regular IO      ; SCLK_from_the_spi_sdcard              ; Dual Purpose Pin          ;
; 200      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO      ; bidir_port_to_and_from_the_pb[3]      ; Dual Purpose Pin          ;
; 201      ; DIFFIO_T20p, PADD6                       ; Use as regular IO      ; bidir_port_to_and_from_the_pb[7]      ; Dual Purpose Pin          ;
; 202      ; DIFFIO_T19n, PADD7                       ; Use as regular IO      ; MOSI_from_the_spi_sdcard              ; Dual Purpose Pin          ;
; 203      ; DIFFIO_T19p, PADD8                       ; Use as regular IO      ; SS_n_from_the_spi_sdcard              ; Dual Purpose Pin          ;
; 207      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO      ; bidir_port_to_and_from_the_pd[7]      ; Dual Purpose Pin          ;
; 214      ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO      ; bidir_port_to_and_from_the_pc[7]      ; Dual Purpose Pin          ;
; 218      ; DIFFIO_T12n, DATA2                       ; Compiler configured    ; bidir_port_to_and_from_the_pc[4]      ; Dual Purpose Pin          ;
; 219      ; DIFFIO_T12p, DATA3                       ; Compiler configured    ; bidir_port_to_and_from_the_pd[2]      ; Dual Purpose Pin          ;
; 220      ; DIFFIO_T11n, PADD18                      ; Use as regular IO      ; SS_n_from_the_spi_lcd22               ; Dual Purpose Pin          ;
; 221      ; DIFFIO_T11p, DATA4                       ; Compiler configured    ; bidir_port_to_and_from_the_pd[6]      ; Dual Purpose Pin          ;
; 222      ; DIFFIO_T10n, PADD19                      ; Use as regular IO      ; bidir_port_to_and_from_the_pc[3]      ; Dual Purpose Pin          ;
; 224      ; DIFFIO_T9n, DATA14, DQS3T/CQ3T#,DPCLK11  ; Use as regular IO      ; MISO_to_the_spi_sdcard                ; Dual Purpose Pin          ;
+----------+------------------------------------------+------------------------+---------------------------------------+---------------------------+


+------------------------------------------------------------+
; I/O Bank Usage                                             ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1        ; 11 / 16 ( 69 % ) ; 3.3V          ; --           ;
; 2        ; 15 / 17 ( 88 % ) ; 3.3V          ; --           ;
; 3        ; 15 / 22 ( 68 % ) ; 3.3V          ; --           ;
; 4        ; 9 / 24 ( 38 % )  ; 3.3V          ; --           ;
; 5        ; 13 / 19 ( 68 % ) ; 3.3V          ; --           ;
; 6        ; 12 / 17 ( 71 % ) ; 3.3V          ; --           ;
; 7        ; 16 / 22 ( 73 % ) ; 3.3V          ; --           ;
; 8        ; 11 / 24 ( 46 % ) ; 3.3V          ; --           ;
+----------+------------------+---------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                    ;
+----------+------------+----------+---------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                        ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+---------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1        ;            ;          ; VCCD_PLL3                             ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 2        ;            ;          ; GNDA3                                 ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 3        ;            ; --       ; VCCA3                                 ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 4        ; 0          ; 1        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 5        ; 1          ; 1        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 6        ; 2          ; 1        ; reset_n                               ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 7        ;            ; 1        ; VCCIO1                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 8        ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 9        ; 6          ; 1        ; zs_dq_to_and_from_the_sdram_0[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 10       ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 11       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 12       ; 9          ; 1        ; sdo_from_the_epcs_flash_controller_0  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; 13       ; 10         ; 1        ; zs_dq_to_and_from_the_sdram_0[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 14       ; 13         ; 1        ; sce_from_the_epcs_flash_controller_0  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; 15       ;            ; 1        ; VCCIO1                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 16       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 17       ; 19         ; 1        ; ^nSTATUS                              ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 18       ; 20         ; 1        ; zs_dq_to_and_from_the_sdram_0[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 19       ; 22         ; 1        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 20       ; 23         ; 1        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 21       ; 24         ; 1        ; zs_dq_to_and_from_the_sdram_0[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 22       ; 27         ; 1        ; zs_dq_to_and_from_the_sdram_0[4]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 23       ; 30         ; 1        ; dclk_from_the_epcs_flash_controller_0 ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; 24       ; 31         ; 1        ; data0_to_the_epcs_flash_controller_0  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; 25       ; 32         ; 1        ; ^nCONFIG                              ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 26       ; 33         ; 1        ; altera_reserved_tdi                   ; input  ; 3.3-V LVTTL  ;         ; --         ; N               ; no       ; Off          ;
; 27       ; 34         ; 1        ; altera_reserved_tck                   ; input  ; 3.3-V LVTTL  ;         ; --         ; N               ; no       ; Off          ;
; 28       ; 35         ; 1        ; altera_reserved_tms                   ; input  ; 3.3-V LVTTL  ;         ; --         ; N               ; no       ; Off          ;
; 29       ; 36         ; 1        ; altera_reserved_tdo                   ; output ; 3.3-V LVTTL  ;         ; --         ; N               ; no       ; Off          ;
; 30       ; 37         ; 1        ; ^nCE                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 31       ; 38         ; 1        ; clk_ex                                ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 32       ; 39         ; 1        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 33       ; 40         ; 2        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 34       ; 41         ; 2        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 35       ;            ; 2        ; VCCIO2                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 36       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 37       ; 49         ; 2        ; zs_dq_to_and_from_the_sdram_0[5]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 38       ; 50         ; 2        ; zs_dq_to_and_from_the_sdram_0[6]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 39       ; 51         ; 2        ; zs_dq_to_and_from_the_sdram_0[7]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 40       ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 41       ; 54         ; 2        ; zs_dqm_from_the_sdram_0[0]            ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 42       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 43       ; 55         ; 2        ; zs_we_n_from_the_sdram_0              ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 44       ; 57         ; 2        ; zs_ras_n_from_the_sdram_0             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 45       ; 58         ; 2        ; zs_cas_n_from_the_sdram_0             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 46       ; 72         ; 2        ; zs_ba_from_the_sdram_0[0]             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 47       ;            ; 2        ; VCCIO2                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 48       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 49       ; 75         ; 2        ; zs_cs_n_from_the_sdram_0              ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 50       ; 76         ; 2        ; zs_addr_from_the_sdram_0[10]          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 51       ; 77         ; 2        ; zs_ba_from_the_sdram_0[1]             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 52       ; 78         ; 2        ; zs_addr_from_the_sdram_0[1]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 53       ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 54       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 55       ; 81         ; 2        ; zs_addr_from_the_sdram_0[0]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 56       ; 82         ; 2        ; zs_addr_from_the_sdram_0[3]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 57       ; 83         ; 2        ; zs_addr_from_the_sdram_0[2]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 58       ;            ; --       ; VCCA1                                 ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 59       ;            ;          ; GNDA1                                 ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 60       ;            ;          ; VCCD_PLL1                             ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 61       ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 62       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 63       ; 96         ; 3        ; in_port_to_the_touch_irq              ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 64       ; 98         ; 3        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 65       ; 99         ; 3        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 66       ;            ; 3        ; VCCIO3                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 67       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 68       ; 101        ; 3        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 69       ; 102        ; 3        ; out_port_from_the_touch_cs            ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 70       ; 103        ; 3        ; MISO_to_the_spi_touch                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 71       ; 104        ; 3        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 72       ; 105        ; 3        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 73       ; 106        ; 3        ; phasedone_from_the_altpll_0           ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 74       ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 75       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 76       ; 119        ; 3        ; bidir_port_to_and_from_the_pc[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 77       ;            ; 3        ; VCCIO3                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 78       ; 120        ; 3        ; MISO_to_the_spi_lcd22                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 79       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 80       ; 122        ; 3        ; bidir_port_to_and_from_the_pc[6]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 81       ; 123        ; 3        ; out_port_from_the_reset               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 82       ; 124        ; 3        ; bidir_port_to_and_from_the_pc[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 83       ; 127        ; 3        ; MOSI_from_the_spi_lcd22               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 84       ; 128        ; 3        ; bidir_port_to_and_from_the_pc[5]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 85       ; 129        ; 3        ; bidir_port_to_and_from_the_pa[6]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 86       ; 130        ; 3        ; bidir_port_to_and_from_the_pd[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 87       ; 131        ; 3        ; bidir_port_to_and_from_the_pc[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 88       ; 132        ; 3        ; SCLK_from_the_spi_lcd22               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 89       ; 134        ; 3        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 90       ; 135        ; 3        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 91       ; 136        ; 4        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 92       ; 137        ; 4        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 93       ; 138        ; 4        ; txd_from_the_uart_9600                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 94       ; 139        ; 4        ; out_port_from_the_lcd_cs              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 95       ; 141        ; 4        ; bidir_port_to_and_from_the_pd[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 96       ;            ; 4        ; VCCIO4                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 97       ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 98       ; 143        ; 4        ; bidir_port_to_and_from_the_pb[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 99       ; 144        ; 4        ; out_port_from_the_lcd_rs              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; On           ;
; 100      ; 145        ; 4        ; locked_from_the_altpll_0              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 101      ; 146        ; 4        ; bidir_port_to_and_from_the_pa[4]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 102      ; 147        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 103      ; 148        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 104      ;            ; 4        ; VCCIO4                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 105      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 106      ; 154        ; 4        ; bidir_port_to_and_from_the_pa[7]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 107      ; 155        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 108      ; 156        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 109      ; 157        ; 4        ; rxd_to_the_uart_9600                  ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 110      ; 163        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 111      ; 164        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 112      ; 165        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 113      ; 167        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 114      ; 168        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 115      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 116      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 117      ; 171        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 118      ; 172        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 119      ; 173        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 120      ; 174        ; 4        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 121      ;            ;          ; VCCD_PLL4                             ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 122      ;            ;          ; GNDA4                                 ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 123      ;            ; --       ; VCCA4                                 ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 124      ;            ; 5        ; VCCIO5                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 125      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 126      ; 181        ; 5        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 127      ; 182        ; 5        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 128      ; 183        ; 5        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 129      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 130      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 131      ; 190        ; 5        ; zs_addr_from_the_sdram_0[4]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 132      ; 191        ; 5        ; zs_addr_from_the_sdram_0[5]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 133      ; 194        ; 5        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 134      ; 202        ; 5        ; zs_addr_from_the_sdram_0[6]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 135      ; 203        ; 5        ; zs_addr_from_the_sdram_0[7]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 136      ;            ; 5        ; VCCIO5                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 137      ; 204        ; 5        ; zs_addr_from_the_sdram_0[8]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 138      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 139      ; 208        ; 5        ; zs_addr_from_the_sdram_0[9]           ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 140      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 141      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 142      ; 214        ; 5        ; zs_addr_from_the_sdram_0[11]          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 143      ; 215        ; 5        ; zs_addr_from_the_sdram_0[12]          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 144      ; 216        ; 5        ; zs_cke_from_the_sdram_0               ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 145      ; 217        ; 5        ; altpll_0_c1_out                       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 146      ; 220        ; 5        ; zs_dqm_from_the_sdram_0[1]            ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 147      ; 221        ; 5        ; bidir_port_to_and_from_the_pa[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
; 148      ; 222        ; 5        ; bidir_port_to_and_from_the_DS18B20    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 149      ; 223        ; 5        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 150      ; 224        ; 5        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 151      ; 225        ; 6        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 152      ; 226        ; 6        ; GND+                                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 153      ; 227        ; 6        ; ^CONF_DONE                            ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 154      ;            ; 6        ; VCCIO6                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 155      ; 228        ; 6        ; ^MSEL0                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 156      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 157      ; 229        ; 6        ; ^MSEL1                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 158      ; 230        ; 6        ; ^MSEL2                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 158      ; 231        ; 6        ; ^MSEL3                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 159      ; 234        ; 6        ; zs_dq_to_and_from_the_sdram_0[8]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 160      ; 235        ; 6        ; zs_dq_to_and_from_the_sdram_0[9]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 161      ; 237        ; 6        ; zs_dq_to_and_from_the_sdram_0[10]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 162      ; 239        ; 6        ; zs_dq_to_and_from_the_sdram_0[11]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 163      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 164      ; 240        ; 6        ; zs_dq_to_and_from_the_sdram_0[12]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 165      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 166      ; 241        ; 6        ; zs_dq_to_and_from_the_sdram_0[13]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 167      ; 255        ; 6        ; bidir_port_to_and_from_the_pd[5]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 168      ; 256        ; 6        ; bidir_port_to_and_from_the_pa[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
; 169      ; 257        ; 6        ; zs_dq_to_and_from_the_sdram_0[14]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 170      ;            ; 6        ; VCCIO6                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 171      ; 260        ; 6        ; zs_dq_to_and_from_the_sdram_0[15]     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 172      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 173      ; 261        ; 6        ; bidir_port_to_and_from_the_pb[5]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
; 174      ; 262        ; 6        ; SCLK_from_the_spi_touch               ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 175      ; 263        ; 6        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 176      ; 270        ; 6        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 177      ; 271        ; 6        ; RESERVED_INPUT                        ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; 178      ;            ; --       ; VCCA2                                 ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 179      ;            ;          ; GNDA2                                 ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 180      ;            ;          ; VCCD_PLL2                             ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 181      ; 275        ; 7        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 182      ; 278        ; 7        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 183      ; 279        ; 7        ; altpll_0_c0_out                       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 184      ; 281        ; 7        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 185      ; 284        ; 7        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 186      ; 285        ; 7        ; bidir_port_to_and_from_the_pa[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 187      ; 289        ; 7        ; bidir_port_to_and_from_the_pa[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 188      ; 290        ; 7        ; bidir_port_to_and_from_the_pa[5]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 189      ; 291        ; 7        ; out_port_from_the_lcd_wr              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 190      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 191      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 192      ;            ; 7        ; VCCIO7                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 193      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 194      ; 297        ; 7        ; out_port_from_the_sd_cs               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 195      ; 300        ; 7        ; bidir_port_to_and_from_the_pb[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 196      ; 301        ; 7        ; SCLK_from_the_spi_sdcard              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 197      ; 302        ; 7        ; bidir_port_to_and_from_the_pb[4]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 198      ; 303        ; 7        ; bidir_port_to_and_from_the_pb[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 199      ; 304        ; 7        ; bidir_port_to_and_from_the_pb[6]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 200      ; 306        ; 7        ; bidir_port_to_and_from_the_pb[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 201      ; 308        ; 7        ; bidir_port_to_and_from_the_pb[7]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 202      ; 309        ; 7        ; MOSI_from_the_spi_sdcard              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 203      ; 310        ; 7        ; SS_n_from_the_spi_sdcard              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 204      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 205      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 206      ;            ; 7        ; VCCIO7                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 207      ; 315        ; 7        ; bidir_port_to_and_from_the_pd[7]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 208      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 209      ; 319        ; 7        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 210      ; 320        ; 7        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 211      ; 321        ; 8        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 212      ; 322        ; 8        ; GND+                                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 213      ;            ; 8        ; VCCIO8                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 214      ; 329        ; 8        ; bidir_port_to_and_from_the_pc[7]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 215      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 216      ; 330        ; 8        ; bidir_port_to_and_from_the_pd[4]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 217      ; 331        ; 8        ; bidir_port_to_and_from_the_pd[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 218      ; 332        ; 8        ; bidir_port_to_and_from_the_pc[4]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 219      ; 333        ; 8        ; bidir_port_to_and_from_the_pd[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 220      ; 334        ; 8        ; SS_n_from_the_spi_lcd22               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 221      ; 335        ; 8        ; bidir_port_to_and_from_the_pd[6]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 222      ; 336        ; 8        ; bidir_port_to_and_from_the_pc[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
; 223      ; 338        ; 8        ; MOSI_from_the_spi_touch               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 224      ; 339        ; 8        ; MISO_to_the_spi_sdcard                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 225      ;            ; 8        ; VCCIO8                                ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 226      ; 345        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 227      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 228      ;            ;          ; VCCINT                                ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 229      ;            ;          ; GND                                   ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 230      ; 347        ; 8        ; SS_n_from_the_spi_touch               ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; On           ;
; 231      ; 348        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 232      ; 349        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 233      ; 352        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 234      ; 354        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 235      ; 356        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 236      ; 359        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 237      ; 360        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 238      ; 361        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 239      ; 362        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; 240      ; 363        ; 8        ; RESERVED_INPUT                        ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+----------+------------+----------+---------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-------------------------------------------------------------------------------------+
; PLL Summary                                                                         ;
+-------------------------------+-----------------------------------------------------+
; Name                          ; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|pll7 ;
+-------------------------------+-----------------------------------------------------+
; SDC pin name                  ; the_altpll_0|sd1|pll7                               ;
; PLL mode                      ; Normal                                              ;
; Compensate clock              ; clock0                                              ;
; Compensated input/output pins ; --                                                  ;
; Switchover type               ; --                                                  ;
; Input frequency 0             ; 50.0 MHz                                            ;
; Input frequency 1             ; --                                                  ;
; Nominal PFD frequency         ; 50.0 MHz                                            ;
; Nominal VCO frequency         ; 450.0 MHz                                           ;
; VCO post scale                ; 2                                                   ;
; VCO frequency control         ; Auto                                                ;
; VCO phase shift step          ; 277 ps                                              ;
; VCO multiply                  ; --                                                  ;
; VCO divide                    ; --                                                  ;
; Freq min lock                 ; 33.34 MHz                                           ;
; Freq max lock                 ; 72.24 MHz                                           ;
; M VCO Tap                     ; 4                                                   ;
; M Initial                     ; 3                                                   ;
; M value                       ; 9                                                   ;
; N value                       ; 1                                                   ;
; Charge pump current           ; setting 1                                           ;
; Loop filter resistance        ; setting 27                                          ;
; Loop filter capacitance       ; setting 0                                           ;
; Bandwidth                     ; 1.03 MHz to 1.97 MHz                                ;
; Bandwidth type                ; Medium                                              ;
; Real time reconfigurable      ; Off                                                 ;
; Scan chain MIF file           ; --                                                  ;
; Preserve PLL counter order    ; Off                                                 ;
; PLL location                  ; PLL_1                                               ;
; Inclk0 signal                 ; clk_ex                                              ;
; Inclk1 signal                 ; --                                                  ;
; Inclk0 signal type            ; Dedicated Pin                                       ;
; Inclk1 signal type            ; --                                                  ;
+-------------------------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage                                                                                                                                                                                                                                                                  ;
+-----------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+------------------------------+
; Name                                                            ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                 ;
+-----------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+------------------------------+
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0] ; clock0       ; 1    ; 1   ; 50.0 MHz         ; 0 (0 ps)        ; 5.00 (277 ps)    ; 50/50      ; C0      ; 9             ; 5/4 Odd    ; --            ; 3       ; 4       ; the_altpll_0|sd1|pll7|clk[0] ;
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[1] ; clock1       ; 1    ; 1   ; 50.0 MHz         ; -100 (-5556 ps) ; 5.00 (277 ps)    ; 50/50      ; C1      ; 9             ; 5/4 Odd    ; --            ; 1       ; 0       ; the_altpll_0|sd1|pll7|clk[1] ;
+-----------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+------------------------------+


+-------------------------------------------------------------------------------+
; Output Pin Default Load For Reported TCO                                      ;
+----------------------------------+-------+------------------------------------+
; I/O Standard                     ; Load  ; Termination Resistance             ;
+----------------------------------+-------+------------------------------------+
; 3.0-V LVTTL                      ; 0 pF  ; Not Available                      ;
; 3.3-V LVTTL                      ; 0 pF  ; Not Available                      ;
; 3.0-V LVCMOS                     ; 0 pF  ; Not Available                      ;
; 3.3-V LVCMOS                     ; 0 pF  ; Not Available                      ;
; 3.0-V PCI                        ; 10 pF ; Not Available                      ;
; 3.0-V PCI-X                      ; 10 pF ; Not Available                      ;
; 2.5 V                            ; 0 pF  ; Not Available                      ;
; 1.8 V                            ; 0 pF  ; Not Available                      ;
; 1.5 V                            ; 0 pF  ; Not Available                      ;
; 1.2 V                            ; 0 pF  ; Not Available                      ;
; SSTL-2 Class I                   ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential 2.5-V SSTL Class I  ; 0 pF  ; (See SSTL-2)                       ;
; SSTL-2 Class II                  ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential 2.5-V SSTL Class II ; 0 pF  ; (See SSTL-2 Class II)              ;
; SSTL-18 Class I                  ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential 1.8-V SSTL Class I  ; 0 pF  ; (See 1.8-V SSTL Class I)           ;
; SSTL-18 Class II                 ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential 1.8-V SSTL Class II ; 0 pF  ; (See 1.8-V SSTL Class II)          ;
; 1.8-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
; Differential 1.8-V HSTL Class I  ; 0 pF  ; (See 1.8-V HSTL Class I)           ;
; 1.8-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
; Differential 1.8-V HSTL Class II ; 0 pF  ; (See 1.8-V HSTL Class II)          ;
; 1.5-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
; Differential 1.5-V HSTL Class I  ; 0 pF  ; (See 1.5-V HSTL Class I)           ;
; 1.5-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
; Differential 1.5-V HSTL Class II ; 0 pF  ; (See 1.5-V HSTL Class II)          ;
; 1.2-V HSTL Class I               ; 0 pF  ; Not Available                      ;
; Differential 1.2-V HSTL Class I  ; 0 pF  ; Not Available                      ;
; 1.2-V HSTL Class II              ; 0 pF  ; Not Available                      ;
; Differential 1.2-V HSTL Class II ; 0 pF  ; Not Available                      ;
; Differential LVPECL              ; 0 pF  ; 100 Ohm (Differential)             ;
; LVDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
; LVDS_E_3R                        ; 0 pF  ; Not Available                      ;
; RSDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
; RSDS_E_1R                        ; 0 pF  ; Not Available                      ;
; RSDS_E_3R                        ; 0 pF  ; Not Available                      ;
; mini-LVDS                        ; 0 pF  ; 100 Ohm (Differential)             ;
; mini-LVDS_E_3R                   ; 0 pF  ; Not Available                      ;
; PPDS                             ; 0 pF  ; Not Available                      ;
; PPDS_E_3R                        ; 0 pF  ; Not Available                      ;
; Bus LVDS                         ; 0 pF  ; Not Available                      ;
+----------------------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                                         ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                                                                  ; Library Name ;
+--------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |nios                                                                                                              ; 4354 (2)    ; 2804 (0)                  ; 69 (69)       ; 55680       ; 13   ; 4            ; 0       ; 2         ; 102  ; 0            ; 1550 (2)     ; 588 (0)           ; 2216 (1)         ; |nios                                                                                                                                                                                                                                ;              ;
;    |DS18B20:the_DS18B20|                                                                                           ; 4 (4)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 3 (3)            ; |nios|DS18B20:the_DS18B20                                                                                                                                                                                                            ;              ;
;    |DS18B20_s1_arbitrator:the_DS18B20_s1|                                                                          ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |nios|DS18B20_s1_arbitrator:the_DS18B20_s1                                                                                                                                                                                           ;              ;
;    |altpll_0:the_altpll_0|                                                                                         ; 9 (5)       ; 6 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 7 (5)            ; |nios|altpll_0:the_altpll_0                                                                                                                                                                                                          ;              ;
;       |altpll_0_altpll_lpa2:sd1|                                                                                   ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; |nios|altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1                                                                                                                                                                                 ;              ;
;       |altpll_0_stdsync_sv6:stdsync2|                                                                              ; 3 (0)       ; 3 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 1 (0)            ; |nios|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2                                                                                                                                                                            ;              ;
;          |altpll_0_dffpipe_l2c:dffpipe3|                                                                           ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 1 (1)            ; |nios|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3                                                                                                                                              ;              ;
;    |cpu:the_cpu|                                                                                                   ; 2370 (1716) ; 1578 (1180)               ; 0 (0)         ; 46464       ; 10   ; 4            ; 0       ; 2         ; 0    ; 0            ; 791 (535)    ; 264 (189)         ; 1315 (952)       ; |nios|cpu:the_cpu                                                                                                                                                                                                                    ;              ;
;       |cpu_bht_module:cpu_bht|                                                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_bht_module:cpu_bht                                                                                                                                                                                             ;              ;
;          |altsyncram:the_altsyncram|                                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram                                                                                                                                                                   ;              ;
;             |altsyncram_2of1:auto_generated|                                                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_2of1:auto_generated                                                                                                                                    ;              ;
;       |cpu_ic_data_module:cpu_ic_data|                                                                             ; 2 (0)       ; 1 (0)                     ; 0 (0)         ; 32768       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 1 (0)            ; |nios|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data                                                                                                                                                                                     ;              ;
;          |altsyncram:the_altsyncram|                                                                               ; 2 (0)       ; 1 (0)                     ; 0 (0)         ; 32768       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 1 (0)            ; |nios|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram                                                                                                                                                           ;              ;
;             |altsyncram_3id1:auto_generated|                                                                       ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 32768       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated                                                                                                                            ;              ;
;       |cpu_ic_tag_module:cpu_ic_tag|                                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2944        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag                                                                                                                                                                                       ;              ;
;          |altsyncram:the_altsyncram|                                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2944        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram                                                                                                                                                             ;              ;
;             |altsyncram_c4g1:auto_generated|                                                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2944        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_c4g1:auto_generated                                                                                                                              ;              ;
;       |cpu_mult_cell:the_cpu_mult_cell|                                                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell                                                                                                                                                                                    ;              ;
;          |altmult_add:the_altmult_add_part_1|                                                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                                 ;              ;
;             |mult_add_dfr2:auto_generated|                                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated                                                                                                                    ;              ;
;                |ded_mult_br81:ded_mult1|                                                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1                                                                                            ;              ;
;          |altmult_add:the_altmult_add_part_2|                                                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                                 ;              ;
;             |mult_add_ffr2:auto_generated|                                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated                                                                                                                    ;              ;
;                |ded_mult_br81:ded_mult1|                                                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1                                                                                            ;              ;
;       |cpu_nios2_oci:the_cpu_nios2_oci|                                                                            ; 616 (32)    ; 397 (0)                   ; 0 (0)         ; 8192        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 178 (32)     ; 75 (0)            ; 363 (0)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci                                                                                                                                                                                    ;              ;
;          |cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|                                         ; 143 (0)     ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 47 (0)       ; 37 (0)            ; 59 (0)           ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper                                                                                                                    ;              ;
;             |cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|                                        ; 50 (46)     ; 49 (45)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 33 (31)           ; 16 (14)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk                                                      ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer2|                                              ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer3|                                              ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;              ;
;             |cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|                                              ; 91 (87)     ; 47 (43)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 44 (44)      ; 4 (1)             ; 43 (43)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck                                                            ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer1|                                              ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1       ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer|                                               ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer        ;              ;
;             |sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|                                                     ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 2 (2)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy                                                                   ;              ;
;          |cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|                                                           ; 14 (14)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 8 (8)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg                                                                                                                                      ;              ;
;          |cpu_nios2_oci_break:the_cpu_nios2_oci_break|                                                             ; 264 (264)   ; 233 (233)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (26)      ; 38 (38)           ; 200 (200)        ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break                                                                                                                                        ;              ;
;          |cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|                                                               ; 207 (44)    ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 52 (23)      ; 0 (0)             ; 155 (21)         ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk                                                                                                                                          ;              ;
;             |cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired|                                      ; 75 (75)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 68 (68)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired                                                                          ;              ;
;             |cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single|                                      ; 45 (45)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 33 (33)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single                                                                          ;              ;
;             |cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit1_match_single|                                      ; 43 (43)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 33 (33)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit1_match_single                                                                          ;              ;
;          |cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|                                                             ; 9 (9)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug                                                                                                                                        ;              ;
;          |cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|                                                               ; 41 (41)     ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 35 (35)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk                                                                                                                                          ;              ;
;          |cpu_nios2_ocimem:the_cpu_nios2_ocimem|                                                                   ; 53 (53)     ; 44 (44)                   ; 0 (0)         ; 8192        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 44 (44)          ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem                                                                                                                                              ;              ;
;             |cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component                                                                   ;              ;
;                |altsyncram:the_altsyncram|                                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                         ;              ;
;                   |altsyncram_6472:auto_generated|                                                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_6472:auto_generated          ;              ;
;       |cpu_register_bank_a_module:cpu_register_bank_a|                                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a                                                                                                                                                                     ;              ;
;          |altsyncram:the_altsyncram|                                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                                                           ;              ;
;             |altsyncram_26f1:auto_generated|                                                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_26f1:auto_generated                                                                                                            ;              ;
;       |cpu_register_bank_b_module:cpu_register_bank_b|                                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b                                                                                                                                                                     ;              ;
;          |altsyncram:the_altsyncram|                                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                                                           ;              ;
;             |altsyncram_36f1:auto_generated|                                                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_36f1:auto_generated                                                                                                            ;              ;
;       |cpu_test_bench:the_cpu_test_bench|                                                                          ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench                                                                                                                                                                                  ;              ;
;       |lpm_add_sub:Add10|                                                                                          ; 66 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 66 (0)       ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|lpm_add_sub:Add10                                                                                                                                                                                                  ;              ;
;          |add_sub_hui:auto_generated|                                                                              ; 66 (66)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 66 (66)      ; 0 (0)             ; 0 (0)            ; |nios|cpu:the_cpu|lpm_add_sub:Add10|add_sub_hui:auto_generated                                                                                                                                                                       ;              ;
;    |cpu_data_master_arbitrator:the_cpu_data_master|                                                                ; 268 (268)   ; 51 (51)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 168 (168)    ; 5 (5)             ; 95 (95)          ; |nios|cpu_data_master_arbitrator:the_cpu_data_master                                                                                                                                                                                 ;              ;
;    |cpu_instruction_master_arbitrator:the_cpu_instruction_master|                                                  ; 97 (97)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 45 (45)      ; 0 (0)             ; 52 (52)          ; |nios|cpu_instruction_master_arbitrator:the_cpu_instruction_master                                                                                                                                                                   ;              ;
;    |cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|                                                    ; 40 (40)     ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 16 (16)          ; |nios|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module                                                                                                                                                                     ;              ;
;    |epcs_flash_controller_0:the_epcs_flash_controller_0|                                                           ; 158 (13)    ; 115 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (12)      ; 38 (0)            ; 78 (1)           ; |nios|epcs_flash_controller_0:the_epcs_flash_controller_0                                                                                                                                                                            ;              ;
;       |altsyncram:the_boot_copier_rom|                                                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom                                                                                                                                             ;              ;
;          |altsyncram_i851:auto_generated|                                                                          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_i851:auto_generated                                                                                                              ;              ;
;       |epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|                                                ; 145 (145)   ; 115 (115)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (30)      ; 38 (38)           ; 77 (77)          ; |nios|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub                                                                                                                ;              ;
;    |epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|            ; 24 (24)     ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 9 (9)            ; |nios|epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port                                                                                                                             ;              ;
;    |jtag_uart_0:the_jtag_uart_0|                                                                                   ; 155 (42)    ; 99 (13)                   ; 0 (0)         ; 1024        ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 56 (29)      ; 12 (0)            ; 87 (12)          ; |nios|jtag_uart_0:the_jtag_uart_0                                                                                                                                                                                                    ;              ;
;       |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|                                                            ; 63 (63)     ; 46 (46)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 12 (12)           ; 35 (35)          ; |nios|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic                                                                                                                                                    ;              ;
;       |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|                                                              ; 26 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r                                                                                                                                                      ;              ;
;          |scfifo:rfifo|                                                                                            ; 26 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                                         ;              ;
;             |scfifo_aq21:auto_generated|                                                                           ; 26 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated                                                                                                              ;              ;
;                |a_dpfifo_h031:dpfifo|                                                                              ; 26 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                         ;              ;
;                   |a_fefifo_7cf:fifo_state|                                                                        ; 14 (8)      ; 8 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 8 (2)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                 ;              ;
;                      |cntr_4n7:count_usedw|                                                                        ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                            ;              ;
;                   |cntr_omb:rd_ptr_count|                                                                          ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                   ;              ;
;                   |cntr_omb:wr_ptr|                                                                                ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                         ;              ;
;                   |dpram_ek21:FIFOram|                                                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                      ;              ;
;                      |altsyncram_i0m1:altsyncram1|                                                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                          ;              ;
;       |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|                                                              ; 25 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w                                                                                                                                                      ;              ;
;          |scfifo:wfifo|                                                                                            ; 25 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                                         ;              ;
;             |scfifo_aq21:auto_generated|                                                                           ; 25 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated                                                                                                              ;              ;
;                |a_dpfifo_h031:dpfifo|                                                                              ; 25 (0)      ; 20 (0)                    ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 20 (0)           ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                         ;              ;
;                   |a_fefifo_7cf:fifo_state|                                                                        ; 13 (7)      ; 8 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 8 (2)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                 ;              ;
;                      |cntr_4n7:count_usedw|                                                                        ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                            ;              ;
;                   |cntr_omb:rd_ptr_count|                                                                          ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                   ;              ;
;                   |cntr_omb:wr_ptr|                                                                                ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                         ;              ;
;                   |dpram_ek21:FIFOram|                                                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                      ;              ;
;                      |altsyncram_i0m1:altsyncram1|                                                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |nios|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                          ;              ;
;    |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|                                    ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |nios|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave                                                                                                                                                     ;              ;
;    |lcd_cs:the_lcd_cs|                                                                                             ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|lcd_cs:the_lcd_cs                                                                                                                                                                                                              ;              ;
;    |lcd_cs_s1_arbitrator:the_lcd_cs_s1|                                                                            ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|lcd_cs_s1_arbitrator:the_lcd_cs_s1                                                                                                                                                                                             ;              ;
;    |lcd_rs:the_lcd_rs|                                                                                             ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|lcd_rs:the_lcd_rs                                                                                                                                                                                                              ;              ;
;    |lcd_rs_s1_arbitrator:the_lcd_rs_s1|                                                                            ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |nios|lcd_rs_s1_arbitrator:the_lcd_rs_s1                                                                                                                                                                                             ;              ;
;    |lcd_wr:the_lcd_wr|                                                                                             ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|lcd_wr:the_lcd_wr                                                                                                                                                                                                              ;              ;
;    |lcd_wr_s1_arbitrator:the_lcd_wr_s1|                                                                            ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|lcd_wr_s1_arbitrator:the_lcd_wr_s1                                                                                                                                                                                             ;              ;
;    |nios_clock_0:the_nios_clock_0|                                                                                 ; 37 (12)     ; 34 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (0)        ; 17 (9)            ; 17 (3)           ; |nios|nios_clock_0:the_nios_clock_0                                                                                                                                                                                                  ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer1|                                                       ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|nios_clock_0:the_nios_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer2|                                                       ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|nios_clock_0:the_nios_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer3|                                                       ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; |nios|nios_clock_0:the_nios_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer|                                                        ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|nios_clock_0:the_nios_clock_0|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                              ;              ;
;       |nios_clock_0_edge_to_pulse:read_done_edge_to_pulse|                                                         ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                               ;              ;
;       |nios_clock_0_edge_to_pulse:read_request_edge_to_pulse|                                                      ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                            ;              ;
;       |nios_clock_0_edge_to_pulse:write_done_edge_to_pulse|                                                        ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                              ;              ;
;       |nios_clock_0_edge_to_pulse:write_request_edge_to_pulse|                                                     ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                           ;              ;
;       |nios_clock_0_master_FSM:master_FSM|                                                                         ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_master_FSM:master_FSM                                                                                                                                                               ;              ;
;       |nios_clock_0_slave_FSM:slave_FSM|                                                                           ; 10 (10)     ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 7 (7)            ; |nios|nios_clock_0:the_nios_clock_0|nios_clock_0_slave_FSM:slave_FSM                                                                                                                                                                 ;              ;
;    |nios_clock_0_in_arbitrator:the_nios_clock_0_in|                                                                ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|nios_clock_0_in_arbitrator:the_nios_clock_0_in                                                                                                                                                                                 ;              ;
;    |nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|                        ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; |nios|nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch                                                                                                                                         ;              ;
;    |nios_reset_clk_ex_domain_synch_module:nios_reset_clk_ex_domain_synch|                                          ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |nios|nios_reset_clk_ex_domain_synch_module:nios_reset_clk_ex_domain_synch                                                                                                                                                           ;              ;
;    |pa:the_pa|                                                                                                     ; 26 (26)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 16 (16)           ; 8 (8)            ; |nios|pa:the_pa                                                                                                                                                                                                                      ;              ;
;    |pa_s1_arbitrator:the_pa_s1|                                                                                    ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|pa_s1_arbitrator:the_pa_s1                                                                                                                                                                                                     ;              ;
;    |pb:the_pb|                                                                                                     ; 26 (26)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 16 (16)           ; 8 (8)            ; |nios|pb:the_pb                                                                                                                                                                                                                      ;              ;
;    |pb_s1_arbitrator:the_pb_s1|                                                                                    ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|pb_s1_arbitrator:the_pb_s1                                                                                                                                                                                                     ;              ;
;    |pc:the_pc|                                                                                                     ; 26 (26)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 16 (16)           ; 8 (8)            ; |nios|pc:the_pc                                                                                                                                                                                                                      ;              ;
;    |pc_s1_arbitrator:the_pc_s1|                                                                                    ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|pc_s1_arbitrator:the_pc_s1                                                                                                                                                                                                     ;              ;
;    |pd:the_pd|                                                                                                     ; 26 (26)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 16 (16)           ; 8 (8)            ; |nios|pd:the_pd                                                                                                                                                                                                                      ;              ;
;    |pd_s1_arbitrator:the_pd_s1|                                                                                    ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |nios|pd_s1_arbitrator:the_pd_s1                                                                                                                                                                                                     ;              ;
;    |reset:the_reset|                                                                                               ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |nios|reset:the_reset                                                                                                                                                                                                                ;              ;
;    |reset_s1_arbitrator:the_reset_s1|                                                                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|reset_s1_arbitrator:the_reset_s1                                                                                                                                                                                               ;              ;
;    |sd_cs:the_sd_cs|                                                                                               ; 2 (2)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |nios|sd_cs:the_sd_cs                                                                                                                                                                                                                ;              ;
;    |sd_cs_s1_arbitrator:the_sd_cs_s1|                                                                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|sd_cs_s1_arbitrator:the_sd_cs_s1                                                                                                                                                                                               ;              ;
;    |sdram_0:the_sdram_0|                                                                                           ; 353 (239)   ; 210 (120)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 142 (136)    ; 45 (2)            ; 166 (78)         ; |nios|sdram_0:the_sdram_0                                                                                                                                                                                                            ;              ;
;       |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|                                                  ; 139 (139)   ; 90 (90)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 43 (43)           ; 90 (90)          ; |nios|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module                                                                                                                                                  ;              ;
;    |sdram_0_s1_arbitrator:the_sdram_0_s1|                                                                          ; 113 (61)    ; 42 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (23)      ; 2 (0)             ; 68 (38)          ; |nios|sdram_0_s1_arbitrator:the_sdram_0_s1                                                                                                                                                                                           ;              ;
;       |rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|               ; 33 (33)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 1 (1)             ; 18 (18)          ; |nios|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1                                                                                              ;              ;
;       |rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1| ; 19 (19)     ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 12 (12)          ; |nios|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1                                                                                ;              ;
;    |sld_hub:auto_hub|                                                                                              ; 130 (86)    ; 76 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 54 (38)      ; 8 (8)             ; 68 (43)          ; |nios|sld_hub:auto_hub                                                                                                                                                                                                               ;              ;
;       |sld_rom_sr:hub_info_reg|                                                                                    ; 24 (24)     ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 9 (9)            ; |nios|sld_hub:auto_hub|sld_rom_sr:hub_info_reg                                                                                                                                                                                       ;              ;
;       |sld_shadow_jsm:shadow_jsm|                                                                                  ; 20 (20)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 19 (19)          ; |nios|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                     ;              ;
;    |spi_lcd22:the_spi_lcd22|                                                                                       ; 142 (142)   ; 117 (117)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (25)      ; 38 (38)           ; 79 (79)          ; |nios|spi_lcd22:the_spi_lcd22                                                                                                                                                                                                        ;              ;
;    |spi_lcd22_spi_control_port_arbitrator:the_spi_lcd22_spi_control_port|                                          ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|spi_lcd22_spi_control_port_arbitrator:the_spi_lcd22_spi_control_port                                                                                                                                                           ;              ;
;    |spi_sdcard:the_spi_sdcard|                                                                                     ; 144 (144)   ; 118 (118)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (26)      ; 38 (38)           ; 80 (80)          ; |nios|spi_sdcard:the_spi_sdcard                                                                                                                                                                                                      ;              ;
;    |spi_sdcard_spi_control_port_arbitrator:the_spi_sdcard_spi_control_port|                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|spi_sdcard_spi_control_port_arbitrator:the_spi_sdcard_spi_control_port                                                                                                                                                         ;              ;
;    |spi_touch:the_spi_touch|                                                                                       ; 146 (146)   ; 120 (120)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (26)      ; 37 (37)           ; 83 (83)          ; |nios|spi_touch:the_spi_touch                                                                                                                                                                                                        ;              ;
;    |spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port|                                          ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port                                                                                                                                                           ;              ;
;    |sysid_control_slave_arbitrator:the_sysid_control_slave|                                                        ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |nios|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                                         ;              ;
;    |touch_cs:the_touch_cs|                                                                                         ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |nios|touch_cs:the_touch_cs                                                                                                                                                                                                          ;              ;
;    |touch_cs_s1_arbitrator:the_touch_cs_s1|                                                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |nios|touch_cs_s1_arbitrator:the_touch_cs_s1                                                                                                                                                                                         ;              ;
;    |touch_irq:the_touch_irq|                                                                                       ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |nios|touch_irq:the_touch_irq                                                                                                                                                                                                        ;              ;
;    |touch_irq_s1_arbitrator:the_touch_irq_s1|                                                                      ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |nios|touch_irq_s1_arbitrator:the_touch_irq_s1                                                                                                                                                                                       ;              ;
;    |uart_9600:the_uart_9600|                                                                                       ; 147 (0)     ; 100 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 47 (0)       ; 17 (0)            ; 83 (0)           ; |nios|uart_9600:the_uart_9600                                                                                                                                                                                                        ;              ;
;       |uart_9600_regs:the_uart_9600_regs|                                                                          ; 48 (48)     ; 29 (29)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 13 (13)           ; 23 (23)          ; |nios|uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs                                                                                                                                                                      ;              ;
;       |uart_9600_rx:the_uart_9600_rx|                                                                              ; 65 (63)     ; 41 (39)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 4 (2)             ; 37 (37)          ; |nios|uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx                                                                                                                                                                          ;              ;
;          |altera_std_synchronizer:the_altera_std_synchronizer|                                                     ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; |nios|uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                      ;              ;
;       |uart_9600_tx:the_uart_9600_tx|                                                                              ; 41 (41)     ; 30 (30)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 30 (30)          ; |nios|uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx                                                                                                                                                                          ;              ;
;    |uart_9600_s1_arbitrator:the_uart_9600_s1|                                                                      ; 5 (5)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 3 (3)            ; |nios|uart_9600_s1_arbitrator:the_uart_9600_s1                                                                                                                                                                                       ;              ;
+--------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                                                            ;
+---------------------------------------+----------+---------------+---------------+-----------------------+----------+----------+
; Name                                  ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO      ; TCOE     ;
+---------------------------------------+----------+---------------+---------------+-----------------------+----------+----------+
; altpll_0_c0_out                       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; altpll_0_c1_out                       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; locked_from_the_altpll_0              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; phasedone_from_the_altpll_0           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; dclk_from_the_epcs_flash_controller_0 ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; sce_from_the_epcs_flash_controller_0  ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; sdo_from_the_epcs_flash_controller_0  ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_lcd_cs              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_lcd_rs              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_lcd_wr              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_reset               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_sd_cs               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; zs_addr_from_the_sdram_0[0]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[1]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[2]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[3]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[4]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[5]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[6]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[7]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[8]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[9]           ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[10]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[11]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_addr_from_the_sdram_0[12]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_ba_from_the_sdram_0[0]             ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_ba_from_the_sdram_0[1]             ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_cas_n_from_the_sdram_0             ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_cke_from_the_sdram_0               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; zs_cs_n_from_the_sdram_0              ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_dqm_from_the_sdram_0[0]            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_dqm_from_the_sdram_0[1]            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_ras_n_from_the_sdram_0             ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; zs_we_n_from_the_sdram_0              ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
; MOSI_from_the_spi_lcd22               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SCLK_from_the_spi_lcd22               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SS_n_from_the_spi_lcd22               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; MOSI_from_the_spi_sdcard              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SCLK_from_the_spi_sdcard              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SS_n_from_the_spi_sdcard              ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; MOSI_from_the_spi_touch               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SCLK_from_the_spi_touch               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; SS_n_from_the_spi_touch               ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; out_port_from_the_touch_cs            ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; txd_from_the_uart_9600                ; Output   ; --            ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_DS18B20    ; Bidir    ; --            ; (6) 2585 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[0]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[1]      ; Bidir    ; --            ; (6) 2585 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[2]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[3]      ; Bidir    ; --            ; (6) 2585 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[4]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[5]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[6]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pa[7]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[0]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[1]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[2]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[3]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[4]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[5]      ; Bidir    ; (6) 2585 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[6]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pb[7]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[0]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[1]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[2]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[3]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[4]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[5]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[6]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pc[7]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[0]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[1]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[2]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[3]      ; Bidir    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[4]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[5]      ; Bidir    ; --            ; (6) 2585 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[6]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; bidir_port_to_and_from_the_pd[7]      ; Bidir    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; zs_dq_to_and_from_the_sdram_0[0]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[1]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[2]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[3]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[4]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[5]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[6]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[7]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[8]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[9]      ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[10]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[11]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[12]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[13]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[14]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; zs_dq_to_and_from_the_sdram_0[15]     ; Bidir    ; --            ; --            ; (0) 0 ps              ; (0) 0 ps ; (0) 0 ps ;
; clk_ex                                ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
; reset_n                               ; Input    ; (6) 2585 ps   ; --            ; --                    ; --       ; --       ;
; in_port_to_the_touch_irq              ; Input    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; MISO_to_the_spi_lcd22                 ; Input    ; --            ; (6) 2587 ps   ; --                    ; --       ; --       ;
; MISO_to_the_spi_touch                 ; Input    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; MISO_to_the_spi_sdcard                ; Input    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
; data0_to_the_epcs_flash_controller_0  ; Input    ; (6) 2585 ps   ; --            ; --                    ; --       ; --       ;
; rxd_to_the_uart_9600                  ; Input    ; (6) 2587 ps   ; --            ; --                    ; --       ; --       ;
+---------------------------------------+----------+---------------+---------------+-----------------------+----------+----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                                                                                                                  ;
+-----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                                                                                                               ; Pad To Core Index ; Setting ;
+-----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
; bidir_port_to_and_from_the_DS18B20                                                                                                ;                   ;         ;
;      - DS18B20:the_DS18B20|read_mux_out~0                                                                                         ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pa[0]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[0]~3                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pa[1]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[1]~2                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pa[2]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[2]~1                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pa[3]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[3]~0                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pa[4]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[4]~7                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pa[5]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[5]~6                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pa[6]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[6]~5                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pa[7]                                                                                                  ;                   ;         ;
;      - pa:the_pa|read_mux_out[7]~4                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[0]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[0]~3                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[1]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[1]~2                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[2]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[2]~1                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pb[3]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[3]~0                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[4]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[4]~7                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[5]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[5]~6                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[6]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[6]~5                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pb[7]                                                                                                  ;                   ;         ;
;      - pb:the_pb|read_mux_out[7]~4                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pc[0]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[0]~3                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pc[1]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[1]~2                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pc[2]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[2]~1                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pc[3]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[3]~0                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pc[4]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[4]~7                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pc[5]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[5]~6                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pc[6]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[6]~5                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pc[7]                                                                                                  ;                   ;         ;
;      - pc:the_pc|read_mux_out[7]~4                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pd[0]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[0]~3                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pd[1]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[1]~2                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pd[2]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[2]~1                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pd[3]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[3]~0                                                                                                ; 0                 ; 6       ;
; bidir_port_to_and_from_the_pd[4]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[4]~7                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pd[5]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[5]~6                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pd[6]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[6]~5                                                                                                ; 1                 ; 6       ;
; bidir_port_to_and_from_the_pd[7]                                                                                                  ;                   ;         ;
;      - pd:the_pd|read_mux_out[7]~4                                                                                                ; 1                 ; 6       ;
; zs_dq_to_and_from_the_sdram_0[0]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[1]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[2]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[3]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[4]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[5]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[6]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[7]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[8]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[9]                                                                                                  ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[10]                                                                                                 ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[11]                                                                                                 ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[12]                                                                                                 ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[13]                                                                                                 ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[14]                                                                                                 ;                   ;         ;
; zs_dq_to_and_from_the_sdram_0[15]                                                                                                 ;                   ;         ;
; clk_ex                                                                                                                            ;                   ;         ;
; reset_n                                                                                                                           ;                   ;         ;
;      - reset_n_sources~0                                                                                                          ; 0                 ; 6       ;
; in_port_to_the_touch_irq                                                                                                          ;                   ;         ;
;      - touch_irq:the_touch_irq|read_mux_out                                                                                       ; 0                 ; 6       ;
; MISO_to_the_spi_lcd22                                                                                                             ;                   ;         ;
;      - spi_lcd22:the_spi_lcd22|MISO_reg~0                                                                                         ; 1                 ; 6       ;
; MISO_to_the_spi_touch                                                                                                             ;                   ;         ;
;      - spi_touch:the_spi_touch|MISO_reg~0                                                                                         ; 0                 ; 6       ;
; MISO_to_the_spi_sdcard                                                                                                            ;                   ;         ;
;      - spi_sdcard:the_spi_sdcard|MISO_reg~0                                                                                       ; 0                 ; 6       ;
; data0_to_the_epcs_flash_controller_0                                                                                              ;                   ;         ;
;      - epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|MISO_reg~0 ; 0                 ; 6       ;
; rxd_to_the_uart_9600                                                                                                              ;                   ;         ;
;      - uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder    ; 0                 ; 6       ;
+-----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                                                                                             ; Location               ; Fan-Out ; Usage                                              ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+
; DS18B20:the_DS18B20|data_dir                                                                                                                                                                     ; FF_X23_Y18_N27         ; 3       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                                                                                                     ; JTAG_X1_Y15_N0         ; 159     ; Clock                                              ; yes    ; Global Clock         ; GCLK1            ; --                        ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                     ; JTAG_X1_Y15_N0         ; 21      ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0]                                                                                                                                  ; PLL_1                  ; 2707    ; Clock                                              ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_locked                                                                                                                                  ; PLL_1                  ; 2       ; Clock                                              ; no     ; --                   ; --               ; --                        ;
; altpll_0:the_altpll_0|prev_reset                                                                                                                                                                 ; FF_X22_Y19_N9          ; 2       ; Async. clear                                       ; yes    ; Global Clock         ; GCLK11           ; --                        ;
; clk_ex                                                                                                                                                                                           ; PIN_31                 ; 24      ; Clock                                              ; yes    ; Global Clock         ; GCLK2            ; --                        ;
; clk_ex                                                                                                                                                                                           ; PIN_31                 ; 2       ; Clock                                              ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_ctrl_ld                                                                                                                                                                            ; FF_X19_Y13_N25         ; 34      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_ctrl_ld32                                                                                                                                                                          ; FF_X19_Y13_N11         ; 27      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_ienable_reg_irq0~0                                                                                                                                                                 ; LCCOMB_X19_Y8_N22      ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_mem_baddr[3]                                                                                                                                                                       ; FF_X22_Y14_N25         ; 92      ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_mul_stall_d3                                                                                                                                                                       ; FF_X22_Y6_N25          ; 32      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_stall~0                                                                                                                                                                            ; LCCOMB_X17_Y7_N16      ; 656     ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|A_wr_dst_reg_from_M                                                                                                                                                                  ; FF_X20_Y10_N11         ; 4       ; Write enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|Add8~5                                                                                                                                                                               ; LCCOMB_X27_Y8_N20      ; 32      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|D_ctrl_src2_choose_imm                                                                                                                                                               ; FF_X14_Y10_N27         ; 33      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|D_ic_fill_starting~1                                                                                                                                                                 ; LCCOMB_X22_Y12_N20     ; 32      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|E_hbreak_req                                                                                                                                                                         ; LCCOMB_X14_Y13_N30     ; 31      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|E_iw[0]                                                                                                                                                                              ; FF_X17_Y13_N9          ; 9       ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|E_iw[4]                                                                                                                                                                              ; FF_X17_Y12_N21         ; 28      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|F_stall                                                                                                                                                                              ; LCCOMB_X16_Y9_N18      ; 176     ; Clock enable, Read enable, Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|M_bht_wr_en_unfiltered                                                                                                                                                               ; LCCOMB_X14_Y9_N24      ; 1       ; Write enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|M_br_cond_taken_history[0]~0                                                                                                                                                         ; LCCOMB_X14_Y9_N28      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|M_pipe_flush                                                                                                                                                                         ; FF_X14_Y9_N31          ; 54      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|M_rot_rn[3]                                                                                                                                                                          ; FF_X27_Y8_N25          ; 32      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|always88~0                                                                                                                                                                           ; LCCOMB_X17_Y7_N0       ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|ram_block1a0~0                                                                               ; LCCOMB_X20_Y8_N6       ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jxuir                  ; FF_X27_Y21_N9          ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_break_a~0  ; LCCOMB_X28_Y17_N10     ; 45      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_a   ; LCCOMB_X27_Y16_N24     ; 15      ; Clock enable, Sync. load                           ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X28_Y19_N24     ; 13      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~1 ; LCCOMB_X28_Y17_N28     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_b   ; LCCOMB_X28_Y17_N20     ; 34      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|update_jdo_strobe      ; FF_X28_Y19_N29         ; 39      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[11]~15                    ; LCCOMB_X29_Y21_N0      ; 13      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[22]~24                    ; LCCOMB_X28_Y21_N20     ; 18      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|virtual_state_sdr~0                 ; LCCOMB_X29_Y21_N18     ; 40      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|virtual_state_uir~0                 ; LCCOMB_X29_Y21_N14     ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0                                                                        ; LCCOMB_X22_Y16_N22     ; 7       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always5~2                                                                                                ; LCCOMB_X24_Y15_N28     ; 27      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always6~0                                                                                                ; LCCOMB_X24_Y15_N18     ; 27      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[0]~1                                                                                               ; LCCOMB_X30_Y17_N4      ; 27      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[32]~0                                                                                              ; LCCOMB_X30_Y17_N26     ; 32      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[69]~2                                                                                              ; LCCOMB_X28_Y17_N22     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[0]~1                                                                                               ; LCCOMB_X30_Y17_N30     ; 27      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[32]~0                                                                                              ; LCCOMB_X30_Y17_N8      ; 32      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[69]~2                                                                                              ; LCCOMB_X30_Y17_N20     ; 7       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|xbrk_ctrl0[0]~0                                                                                          ; LCCOMB_X28_Y17_N26     ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|xbrk_ctrl1[0]~0                                                                                          ; LCCOMB_X30_Y17_N24     ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[0]~15                                                                                                  ; LCCOMB_X28_Y19_N10     ; 31      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr                                                                                                          ; FF_X30_Y18_N27         ; 3       ; Write enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|comb~0                                                                                                         ; LCCOMB_X22_Y16_N14     ; 2       ; Write enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|i_readdatavalid_d1                                                                                                                                                                   ; FF_X20_Y15_N9          ; 7       ; Clock enable, Write enable                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_fill_ap_offset[1]~0                                                                                                                                                               ; LCCOMB_X22_Y12_N14     ; 7       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_fill_dp_offset_en~0                                                                                                                                                               ; LCCOMB_X14_Y12_N28     ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_fill_valid_bits_en                                                                                                                                                                ; LCCOMB_X14_Y12_N0      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_tag_clr_valid_bits_nxt~2                                                                                                                                                          ; LCCOMB_X19_Y13_N18     ; 7       ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_tag_wraddress[1]~6                                                                                                                                                                ; LCCOMB_X19_Y13_N20     ; 6       ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; cpu:the_cpu|ic_tag_wren                                                                                                                                                                          ; LCCOMB_X12_Y12_N16     ; 1       ; Write enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu_data_master_arbitrator:the_cpu_data_master|always3~0                                                                                                                                         ; LCCOMB_X23_Y18_N6      ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; cpu_instruction_master_arbitrator:the_cpu_instruction_master|always2~0                                                                                                                           ; LCCOMB_X19_Y16_N30     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|always11~0                                                                       ; LCCOMB_X11_Y19_N0      ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|always6~0                                                                        ; LCCOMB_X14_Y16_N24     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|control_wr_strobe                                                                ; LCCOMB_X15_Y16_N26     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_wr_strobe                                                       ; LCCOMB_X15_Y16_N28     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|shift_reg[1]~1                                                                   ; LCCOMB_X11_Y19_N4      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|slaveselect_wr_strobe                                                            ; LCCOMB_X15_Y16_N20     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|transmitting~0                                                                   ; LCCOMB_X11_Y19_N26     ; 11      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|write_tx_holding                                                                 ; LCCOMB_X11_Y19_N6      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena~0                                                                                                              ; LCCOMB_X30_Y20_N30     ; 1       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write~0                                                                                                         ; LCCOMB_X30_Y21_N16     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4                                                                                                        ; LCCOMB_X29_Y21_N28     ; 21      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled~1                                                                                                      ; LCCOMB_X29_Y21_N8      ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|fifo_wr                                                                                                                                                              ; FF_X24_Y20_N21         ; 15      ; Clock enable, Write enable                         ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|ien_AE~0                                                                                                                                                             ; LCCOMB_X20_Y19_N8      ; 3       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|_~4                               ; LCCOMB_X29_Y20_N14     ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|_~0                               ; LCCOMB_X24_Y19_N0      ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|r_val~0                                                                                                                                                              ; LCCOMB_X24_Y20_N24     ; 11      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|rvalid~0                                                                                                                                                             ; LCCOMB_X29_Y20_N18     ; 11      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; jtag_uart_0:the_jtag_uart_0|wr_rfifo                                                                                                                                                             ; LCCOMB_X29_Y20_N30     ; 13      ; Clock enable, Write enable                         ; no     ; --                   ; --               ; --                        ;
; nios_clock_0:the_nios_clock_0|nios_clock_0_master_FSM:master_FSM|master_read                                                                                                                     ; FF_X22_Y19_N25         ; 3       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|data_out                                                                                                  ; FF_X32_Y10_N17         ; 2227    ; Async. clear, Async. load                          ; yes    ; Global Clock         ; GCLK10           ; --                        ;
; nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|data_out                                                                                                  ; FF_X32_Y10_N17         ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; nios_reset_clk_ex_domain_synch_module:nios_reset_clk_ex_domain_synch|data_out                                                                                                                    ; FF_X20_Y28_N1          ; 22      ; Async. clear                                       ; yes    ; Global Clock         ; GCLK14           ; --                        ;
; pa:the_pa|always1~0                                                                                                                                                                              ; LCCOMB_X21_Y18_N22     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|always2~0                                                                                                                                                                              ; LCCOMB_X21_Y18_N16     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[0]                                                                                                                                                                            ; FF_X32_Y20_N3          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[1]                                                                                                                                                                            ; FF_X32_Y20_N13         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[2]                                                                                                                                                                            ; FF_X32_Y20_N7          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[3]                                                                                                                                                                            ; FF_X32_Y20_N1          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[4]                                                                                                                                                                            ; FF_X19_Y20_N11         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[5]                                                                                                                                                                            ; FF_X32_Y20_N11         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[6]                                                                                                                                                                            ; FF_X19_Y20_N5          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pa:the_pa|data_dir[7]                                                                                                                                                                            ; FF_X32_Y20_N29         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|always1~0                                                                                                                                                                              ; LCCOMB_X20_Y18_N20     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|always2~0                                                                                                                                                                              ; LCCOMB_X21_Y18_N18     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[0]                                                                                                                                                                            ; FF_X26_Y24_N3          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[1]                                                                                                                                                                            ; FF_X26_Y24_N5          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[2]                                                                                                                                                                            ; FF_X26_Y24_N7          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[3]                                                                                                                                                                            ; FF_X26_Y24_N1          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[4]                                                                                                                                                                            ; FF_X26_Y24_N11         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[5]                                                                                                                                                                            ; FF_X26_Y24_N21         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[6]                                                                                                                                                                            ; FF_X26_Y24_N15         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pb:the_pb|data_dir[7]                                                                                                                                                                            ; FF_X26_Y24_N25         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|always1~0                                                                                                                                                                              ; LCCOMB_X23_Y18_N0      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|always2~0                                                                                                                                                                              ; LCCOMB_X23_Y18_N2      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[0]                                                                                                                                                                            ; FF_X15_Y18_N23         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[1]                                                                                                                                                                            ; FF_X15_Y18_N1          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[2]                                                                                                                                                                            ; FF_X15_Y18_N19         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[3]                                                                                                                                                                            ; FF_X15_Y18_N29         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[4]                                                                                                                                                                            ; FF_X15_Y18_N15         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[5]                                                                                                                                                                            ; FF_X15_Y18_N9          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[6]                                                                                                                                                                            ; FF_X15_Y18_N27         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pc:the_pc|data_dir[7]                                                                                                                                                                            ; FF_X15_Y18_N13         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|always1~0                                                                                                                                                                              ; LCCOMB_X23_Y18_N4      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|always2~0                                                                                                                                                                              ; LCCOMB_X23_Y18_N22     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[0]                                                                                                                                                                            ; FF_X16_Y18_N5          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[1]                                                                                                                                                                            ; FF_X14_Y21_N31         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[2]                                                                                                                                                                            ; FF_X14_Y21_N1          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[3]                                                                                                                                                                            ; FF_X14_Y21_N3          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[4]                                                                                                                                                                            ; FF_X14_Y21_N29         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[5]                                                                                                                                                                            ; FF_X16_Y18_N23         ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[6]                                                                                                                                                                            ; FF_X14_Y21_N7          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; pd:the_pd|data_dir[7]                                                                                                                                                                            ; FF_X14_Y21_N9          ; 2       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; reset_n_sources~0                                                                                                                                                                                ; LCCOMB_X24_Y18_N0      ; 4       ; Async. clear                                       ; yes    ; Global Clock         ; GCLK12           ; --                        ;
; sdram_0:the_sdram_0|Selector27~6                                                                                                                                                                 ; LCCOMB_X32_Y10_N10     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|Selector34~4                                                                                                                                                                 ; LCCOMB_X33_Y10_N20     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|WideOr16~0                                                                                                                                                                   ; LCCOMB_X33_Y12_N0      ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|active_rnw~1                                                                                                                                                                 ; LCCOMB_X32_Y10_N16     ; 43      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|f_select                                                                                                                                                                     ; LCCOMB_X30_Y10_N6      ; 24      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|m_addr[1]~4                                                                                                                                                                  ; LCCOMB_X33_Y12_N30     ; 13      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|m_state.000000010                                                                                                                                                            ; FF_X32_Y10_N27         ; 32      ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|m_state.000010000                                                                                                                                                            ; FF_X32_Y12_N11         ; 59      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|m_state.001000000                                                                                                                                                            ; FF_X31_Y10_N19         ; 21      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe                                                                                                                                                                           ; DDIOOECELL_X0_Y25_N19  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_1                                                                                                                                                              ; DDIOOECELL_X0_Y26_N19  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_10                                                                                                                                                             ; DDIOOECELL_X41_Y18_N5  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_11                                                                                                                                                             ; DDIOOECELL_X41_Y19_N19 ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_12                                                                                                                                                             ; DDIOOECELL_X41_Y19_N12 ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_13                                                                                                                                                             ; DDIOOECELL_X41_Y19_N5  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_14                                                                                                                                                             ; DDIOOECELL_X41_Y23_N5  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_15                                                                                                                                                             ; DDIOOECELL_X41_Y24_N12 ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_2                                                                                                                                                              ; DDIOOECELL_X0_Y22_N5   ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_3                                                                                                                                                              ; DDIOOECELL_X0_Y21_N5   ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_4                                                                                                                                                              ; DDIOOECELL_X0_Y21_N26  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_5                                                                                                                                                              ; DDIOOECELL_X0_Y12_N26  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_6                                                                                                                                                              ; DDIOOECELL_X0_Y11_N5   ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_7                                                                                                                                                              ; DDIOOECELL_X0_Y11_N12  ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_8                                                                                                                                                              ; DDIOOECELL_X41_Y18_N26 ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|oe~_Duplicate_9                                                                                                                                                              ; DDIOOECELL_X41_Y18_N19 ; 1       ; Output enable                                      ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[42]~2                                                                                                      ; LCCOMB_X32_Y11_N10     ; 43      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[42]~2                                                                                                      ; LCCOMB_X32_Y11_N8      ; 43      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always0~0                                                      ; LCCOMB_X37_Y12_N22     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always10~0                                                     ; LCCOMB_X37_Y12_N26     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always12~0                                                     ; LCCOMB_X37_Y12_N14     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always1~0                                                      ; LCCOMB_X37_Y12_N4      ; 7       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always2~0                                                      ; LCCOMB_X37_Y12_N28     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always4~0                                                      ; LCCOMB_X37_Y12_N8      ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always6~0                                                      ; LCCOMB_X37_Y12_N20     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always8~0                                                      ; LCCOMB_X37_Y12_N16     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1|always15~0                                       ; LCCOMB_X37_Y12_N0      ; 10      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_counter_enable~0                                                                                                                             ; LCCOMB_X31_Y11_N14     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_winner~2                                                                                                                                     ; LCCOMB_X30_Y11_N14     ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|clr_reg                                                                                                                                                                         ; FF_X31_Y24_N11         ; 68      ; Async. clear                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|irf_reg[1][0]~5                                                                                                                                                                 ; LCCOMB_X33_Y24_N26     ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|irf_reg[2][0]~12                                                                                                                                                                ; LCCOMB_X33_Y24_N6      ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|irsr_reg[2]~3                                                                                                                                                                   ; LCCOMB_X30_Y24_N10     ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|node_ena~3                                                                                                                                                                      ; LCCOMB_X33_Y24_N4      ; 2       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|shadow_irf_reg[1][0]~2                                                                                                                                                          ; LCCOMB_X30_Y24_N2      ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|shadow_irf_reg[2][0]~9                                                                                                                                                          ; LCCOMB_X30_Y24_N30     ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]~7                                                                                                                                            ; LCCOMB_X35_Y22_N24     ; 4       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]~10                                                                                                                                      ; LCCOMB_X36_Y22_N2      ; 5       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]~19                                                                                                                                      ; LCCOMB_X36_Y22_N4      ; 5       ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                              ; FF_X31_Y23_N15         ; 15      ; Async. clear                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                             ; FF_X32_Y23_N7          ; 12      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                              ; FF_X31_Y23_N27         ; 35      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                              ; FF_X32_Y23_N3          ; 39      ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                              ; FF_X32_Y24_N19         ; 11      ; Async. clear                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|virtual_ir_dr_scan_proc~0                                                                                                                                                       ; LCCOMB_X31_Y23_N24     ; 3       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|virtual_ir_scan_reg                                                                                                                                                             ; FF_X31_Y23_N5          ; 26      ; Async. clear                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|always11~0                                                                                                                                                               ; LCCOMB_X20_Y21_N14     ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|always6~0                                                                                                                                                                ; LCCOMB_X21_Y22_N16     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|control_wr_strobe                                                                                                                                                        ; LCCOMB_X19_Y21_N20     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_wr_strobe~0                                                                                                                                             ; LCCOMB_X19_Y21_N12     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|shift_reg[0]~10                                                                                                                                                          ; LCCOMB_X19_Y21_N6      ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|slaveselect_wr_strobe~0                                                                                                                                                  ; LCCOMB_X19_Y21_N4      ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|transmitting~3                                                                                                                                                           ; LCCOMB_X20_Y21_N8      ; 11      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_lcd22:the_spi_lcd22|write_tx_holding                                                                                                                                                         ; LCCOMB_X19_Y21_N24     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|always11~0                                                                                                                                                             ; LCCOMB_X23_Y24_N24     ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|always6~0                                                                                                                                                              ; LCCOMB_X16_Y24_N16     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|control_wr_strobe                                                                                                                                                      ; LCCOMB_X23_Y24_N16     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_wr_strobe~0                                                                                                                                           ; LCCOMB_X23_Y24_N6      ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|shift_reg[0]~10                                                                                                                                                        ; LCCOMB_X23_Y24_N30     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|slaveselect_wr_strobe~0                                                                                                                                                ; LCCOMB_X23_Y24_N28     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|transmitting~3                                                                                                                                                         ; LCCOMB_X21_Y26_N28     ; 11      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_sdcard:the_spi_sdcard|write_tx_holding                                                                                                                                                       ; LCCOMB_X23_Y24_N22     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|always11~0                                                                                                                                                               ; LCCOMB_X14_Y22_N18     ; 6       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|always6~0                                                                                                                                                                ; LCCOMB_X16_Y22_N8      ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|control_wr_strobe                                                                                                                                                        ; LCCOMB_X17_Y22_N14     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|endofpacketvalue_wr_strobe~0                                                                                                                                             ; LCCOMB_X17_Y22_N30     ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|p1_slowcount~1                                                                                                                                                           ; LCCOMB_X14_Y22_N4      ; 5       ; Sync. clear                                        ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|shift_reg[4]~11                                                                                                                                                          ; LCCOMB_X17_Y22_N24     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|slaveselect_wr_strobe~0                                                                                                                                                  ; LCCOMB_X17_Y22_N0      ; 16      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|transmitting~8                                                                                                                                                           ; LCCOMB_X14_Y22_N30     ; 10      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; spi_touch:the_spi_touch|write_tx_holding                                                                                                                                                         ; LCCOMB_X17_Y22_N12     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs|control_wr_strobe~0                                                                                                                    ; LCCOMB_X22_Y18_N10     ; 10      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs|tx_wr_strobe~0                                                                                                                         ; LCCOMB_X22_Y18_N28     ; 8       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|got_new_char                                                                                                                               ; LCCOMB_X31_Y18_N10     ; 10      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]~0                                                                                   ; LCCOMB_X31_Y22_N6      ; 10      ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|always4~0                                                                                                                                  ; LCCOMB_X32_Y18_N14     ; 13      ; Sync. load                                         ; no     ; --                   ; --               ; --                        ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~1                                                                            ; LCCOMB_X32_Y13_N20     ; 9       ; Clock enable                                       ; no     ; --                   ; --               ; --                        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                            ; Location          ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; altera_internal_jtag~TCKUTAP                                                                    ; JTAG_X1_Y15_N0    ; 159     ; 0                                    ; Global Clock         ; GCLK1            ; --                        ;
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0]                                 ; PLL_1             ; 2707    ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[1]                                 ; PLL_1             ; 1       ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
; altpll_0:the_altpll_0|prev_reset                                                                ; FF_X22_Y19_N9     ; 2       ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
; clk_ex                                                                                          ; PIN_31            ; 24      ; 0                                    ; Global Clock         ; GCLK2            ; --                        ;
; nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|data_out ; FF_X32_Y10_N17    ; 2227    ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
; nios_reset_clk_ex_domain_synch_module:nios_reset_clk_ex_domain_synch|data_out                   ; FF_X20_Y28_N1     ; 22      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
; reset_n_sources~0                                                                               ; LCCOMB_X24_Y18_N0 ; 4       ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+-------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                                                                                                                  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                                                                                   ; Fan-Out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; cpu:the_cpu|A_stall~0                                                                                                                                                                                  ; 656     ;
; cpu:the_cpu|F_stall                                                                                                                                                                                    ; 177     ;
; cpu:the_cpu|A_mem_baddr[2]                                                                                                                                                                             ; 137     ;
; cpu:the_cpu|A_mem_baddr[3]                                                                                                                                                                             ; 92      ;
; cpu:the_cpu|A_mul_stall                                                                                                                                                                                ; 73      ;
; sld_hub:auto_hub|clr_reg                                                                                                                                                                               ; 68      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_d_write                                                                                                      ; 66      ;
; sdram_0:the_sdram_0|m_state.000010000                                                                                                                                                                  ; 59      ;
; cpu:the_cpu|A_mem_baddr[4]                                                                                                                                                                             ; 57      ;
; cpu:the_cpu|M_pipe_flush                                                                                                                                                                               ; 54      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_select~0                                                                                                                                      ; 54      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_data_master_requests_sdram_0_s1                                                                                                                               ; 53      ;
; jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_0_avalon_jtag_slave                                                                      ; 52      ;
; nios_clock_0_in_arbitrator:the_nios_clock_0_in|cpu_data_master_requests_nios_clock_0_in                                                                                                                ; 52      ;
; cpu:the_cpu|E_src1[5]~1                                                                                                                                                                                ; 48      ;
; cpu:the_cpu|E_src1[5]~0                                                                                                                                                                                ; 48      ;
; cpu:the_cpu|A_wr_data_unfiltered[27]~1                                                                                                                                                                 ; 48      ;
; cpu:the_cpu|A_wr_data_unfiltered[27]~0                                                                                                                                                                 ; 48      ;
; cpu:the_cpu|D_src2_reg[17]~31                                                                                                                                                                          ; 48      ;
; cpu:the_cpu|D_src2_reg[17]~30                                                                                                                                                                          ; 48      ;
; sld_hub:auto_hub|irf_reg[1][1]                                                                                                                                                                         ; 46      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_break_a~0        ; 45      ;
; cpu:the_cpu|F_iw[3]~39                                                                                                                                                                                 ; 44      ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address                                                                                                               ; 44      ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[42]~2                                                                                                            ; 43      ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[42]~2                                                                                                            ; 43      ;
; sdram_0:the_sdram_0|active_rnw~1                                                                                                                                                                       ; 43      ;
; cpu:the_cpu|A_st_data[0]                                                                                                                                                                               ; 43      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|cpu_instruction_master_qualified_request_epcs_flash_controller_0_epcs_control_port                  ; 42      ;
; cpu:the_cpu|d_write                                                                                                                                                                                    ; 42      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_data_master_granted_sdram_0_s1~0                                                                                                                              ; 41      ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~0                                                                                                          ; 40      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|virtual_state_sdr~0                       ; 40      ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                    ; 39      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|update_jdo_strobe            ; 39      ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~0                                                                                                                                                                  ; 38      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|cpu_data_master_requests_epcs_flash_controller_0_epcs_control_port                                  ; 38      ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~1                                                                                                                                                                  ; 37      ;
; cpu:the_cpu|A_st_data[3]                                                                                                                                                                               ; 37      ;
; cpu:the_cpu|D_ctrl_a_not_src                                                                                                                                                                           ; 37      ;
; sdram_0:the_sdram_0|za_valid                                                                                                                                                                           ; 37      ;
; cpu:the_cpu|d_read                                                                                                                                                                                     ; 37      ;
; spi_touch:the_spi_touch|data_to_cpu[6]~0                                                                                                                                                               ; 36      ;
; cpu:the_cpu|A_st_data[4]                                                                                                                                                                               ; 36      ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                    ; 35      ;
; cpu:the_cpu|A_st_data[1]                                                                                                                                                                               ; 35      ;
; cpu:the_cpu|A_st_data[6]                                                                                                                                                                               ; 35      ;
; cpu:the_cpu|A_st_data[7]                                                                                                                                                                               ; 35      ;
; cpu:the_cpu|A_ctrl_ld                                                                                                                                                                                  ; 34      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_b         ; 34      ;
; cpu:the_cpu|E_ctrl_alu_subtract                                                                                                                                                                        ; 34      ;
; cpu:the_cpu|E_regnum_a_cmp_D                                                                                                                                                                           ; 34      ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_in_a_read_cycle~3                                                                                                     ; 33      ;
; cpu:the_cpu|D_ctrl_src2_choose_imm                                                                                                                                                                     ; 33      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[32]                      ; 33      ;
; cpu:the_cpu|E_ctrl_logic                                                                                                                                                                               ; 33      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10]                                                                                                          ; 33      ;
; cpu:the_cpu|M_rot_rn[3]                                                                                                                                                                                ; 32      ;
; cpu:the_cpu|M_rot_rn[2]                                                                                                                                                                                ; 32      ;
; cpu:the_cpu|M_rot_rn[4]                                                                                                                                                                                ; 32      ;
; cpu:the_cpu|A_mul_stall_d3                                                                                                                                                                             ; 32      ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module                                                                                              ; 32      ;
; cpu:the_cpu|M_ctrl_rdctl_inst                                                                                                                                                                          ; 32      ;
; cpu:the_cpu|A_rot_fill_bit                                                                                                                                                                             ; 32      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[32]~0                                                                                                    ; 32      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[32]~0                                                                                                    ; 32      ;
; cpu:the_cpu|D_ctrl_hi_imm16                                                                                                                                                                            ; 32      ;
; cpu:the_cpu|A_st_data[5]                                                                                                                                                                               ; 32      ;
; cpu:the_cpu|A_st_data[2]                                                                                                                                                                               ; 32      ;
; cpu:the_cpu|E_logic_op[0]                                                                                                                                                                              ; 32      ;
; cpu:the_cpu|E_logic_op[1]                                                                                                                                                                              ; 32      ;
; cpu:the_cpu|E_alu_result~0                                                                                                                                                                             ; 32      ;
; cpu:the_cpu|D_ic_fill_starting~1                                                                                                                                                                       ; 32      ;
; sdram_0:the_sdram_0|m_state.000000010                                                                                                                                                                  ; 32      ;
; cpu:the_cpu|Add8~5                                                                                                                                                                                     ; 32      ;
; cpu:the_cpu|Add8~3                                                                                                                                                                                     ; 32      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[0]~15                                                                                                        ; 31      ;
; cpu:the_cpu|E_hbreak_req                                                                                                                                                                               ; 31      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_address[0]~1                                              ; 31      ;
; cpu:the_cpu|A_mem_baddr[5]                                                                                                                                                                             ; 29      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0     ; 28      ;
; cpu:the_cpu|E_iw[4]                                                                                                                                                                                    ; 28      ;
; sld_hub:auto_hub|irf_reg[1][0]                                                                                                                                                                         ; 27      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[0]~1                                                                                                     ; 27      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[0]~1                                                                                                     ; 27      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always5~2                                                                                                      ; 27      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always6~0                                                                                                      ; 27      ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_grant_vector[1]~1                                                                                                     ; 27      ;
; cpu:the_cpu|A_ctrl_ld32                                                                                                                                                                                ; 27      ;
; cpu:the_cpu|D_bht_data[1]                                                                                                                                                                              ; 27      ;
; sld_hub:auto_hub|virtual_ir_scan_reg                                                                                                                                                                   ; 26      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[10]~9                                                                                                                                             ; 26      ;
; cpu:the_cpu|E_ctrl_exception                                                                                                                                                                           ; 26      ;
; cpu:the_cpu|E_ctrl_crst                                                                                                                                                                                ; 26      ;
; cpu:the_cpu|E_ctrl_break                                                                                                                                                                               ; 26      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg~7                                                                                                ; 26      ;
; cpu:the_cpu|E_ctrl_br_cond_nxt~1                                                                                                                                                                       ; 26      ;
; cpu:the_cpu|E_valid_jmp_indirect                                                                                                                                                                       ; 26      ;
; cpu:the_cpu|E_ctrl_retaddr                                                                                                                                                                             ; 26      ;
; cpu:the_cpu|E_ctrl_jmp_indirect                                                                                                                                                                        ; 25      ;
; cpu:the_cpu|D_ctrl_b_is_dst                                                                                                                                                                            ; 25      ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_dbs_address[1]                                                                                                                          ; 25      ;
; cpu:the_cpu|A_mem_baddr[7]                                                                                                                                                                             ; 25      ;
; spi_lcd22:the_spi_lcd22|p1_data_to_cpu[2]~3                                                                                                                                                            ; 24      ;
; cpu:the_cpu|A_slow_ld_data_fill_bit                                                                                                                                                                    ; 24      ;
; cpu:the_cpu|D_iw[12]                                                                                                                                                                                   ; 24      ;
; sdram_0:the_sdram_0|refresh_request                                                                                                                                                                    ; 24      ;
; sdram_0:the_sdram_0|f_select                                                                                                                                                                           ; 24      ;
; cpu:the_cpu|D_iw[14]                                                                                                                                                                                   ; 23      ;
; cpu:the_cpu|A_mem_baddr[6]                                                                                                                                                                             ; 23      ;
; sld_hub:auto_hub|hub_mode_reg[1]                                                                                                                                                                       ; 22      ;
; sdram_0:the_sdram_0|m_state.000000001                                                                                                                                                                  ; 22      ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                           ; 21      ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4                                                                                                              ; 21      ;
; sdram_0:the_sdram_0|m_state.001000000                                                                                                                                                                  ; 21      ;
; cpu:the_cpu|A_st_data[10]                                                                                                                                                                              ; 21      ;
; cpu:the_cpu|E_ctrl_shift_rot_right                                                                                                                                                                     ; 20      ;
; spi_sdcard:the_spi_sdcard|data_to_cpu[5]~0                                                                                                                                                             ; 20      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_instruction_master_read_data_valid_sdram_0_s1                                                                                                                 ; 20      ;
; cpu:the_cpu|D_iw[21]                                                                                                                                                                                   ; 20      ;
; spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port|cpu_data_master_granted_spi_touch_spi_control_port                                                                                ; 20      ;
; spi_sdcard_spi_control_port_arbitrator:the_spi_sdcard_spi_control_port|cpu_data_master_granted_spi_sdcard_spi_control_port                                                                             ; 20      ;
; spi_lcd22_spi_control_port_arbitrator:the_spi_lcd22_spi_control_port|cpu_data_master_granted_spi_lcd22_spi_control_port                                                                                ; 20      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1|fifo_contains_ones_n                                   ; 20      ;
; cpu:the_cpu|D_iw[13]                                                                                                                                                                                   ; 19      ;
; sdram_0:the_sdram_0|WideOr9~0                                                                                                                                                                          ; 19      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_address[2]~2                                              ; 19      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[22]~24                          ; 18      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr~22                              ; 18      ;
; cpu:the_cpu|D_iw[16]                                                                                                                                                                                   ; 18      ;
; cpu:the_cpu|D_iw[15]                                                                                                                                                                                   ; 18      ;
; uart_9600_s1_arbitrator:the_uart_9600_s1|cpu_data_master_granted_uart_9600_s1                                                                                                                          ; 18      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1|stage_0                                                ; 18      ;
; sdram_0:the_sdram_0|always5~0                                                                                                                                                                          ; 18      ;
; sdram_0:the_sdram_0|init_done                                                                                                                                                                          ; 18      ;
; uart_9600_s1_arbitrator:the_uart_9600_s1|cpu_data_master_granted_uart_9600_s1~3                                                                                                                        ; 18      ;
; cpu:the_cpu|E_regnum_b_cmp_D                                                                                                                                                                           ; 18      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                      ; 17      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~0                                                                                                                                              ; 17      ;
; cpu:the_cpu|A_st_data[8]                                                                                                                                                                               ; 17      ;
; cpu:the_cpu|D_src2_hazard_E                                                                                                                                                                            ; 17      ;
; cpu:the_cpu|D_iw[11]                                                                                                                                                                                   ; 17      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[35]                      ; 17      ;
; cpu:the_cpu|A_st_data[9]                                                                                                                                                                               ; 17      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_instruction_master_granted_sdram_0_s1~0                                                                                                                       ; 17      ;
; spi_sdcard:the_spi_sdcard|Equal2~0                                                                                                                                                                     ; 17      ;
; altera_internal_jtag~TDIUTAP                                                                                                                                                                           ; 16      ;
; cpu_instruction_master_arbitrator:the_cpu_instruction_master|always2~0                                                                                                                                 ; 16      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_wr_strobe                                                             ; 16      ;
; spi_touch:the_spi_touch|endofpacketvalue_wr_strobe~0                                                                                                                                                   ; 16      ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_wr_strobe~0                                                                                                                                                   ; 16      ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_wr_strobe~0                                                                                                                                                 ; 16      ;
; cpu_data_master_arbitrator:the_cpu_data_master|always3~0                                                                                                                                               ; 16      ;
; jtag_uart_0:the_jtag_uart_0|read_0                                                                                                                                                                     ; 16      ;
; cpu:the_cpu|A_ld_align_byte2_byte3_fill                                                                                                                                                                ; 16      ;
; jtag_uart_0:the_jtag_uart_0|fifo_wr                                                                                                                                                                    ; 16      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[36]                      ; 16      ;
; cpu:the_cpu|Equal171~1                                                                                                                                                                                 ; 16      ;
; spi_touch:the_spi_touch|slaveselect_wr_strobe~0                                                                                                                                                        ; 16      ;
; spi_sdcard:the_spi_sdcard|slaveselect_wr_strobe~0                                                                                                                                                      ; 16      ;
; spi_lcd22:the_spi_lcd22|slaveselect_wr_strobe~0                                                                                                                                                        ; 16      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|comb~0                                                                                                                                                            ; 16      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|slaveselect_wr_strobe                                                                  ; 16      ;
; spi_touch:the_spi_touch|always6~0                                                                                                                                                                      ; 16      ;
; spi_sdcard:the_spi_sdcard|always6~0                                                                                                                                                                    ; 16      ;
; spi_lcd22:the_spi_lcd22|always6~0                                                                                                                                                                      ; 16      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|always6~0                                                                              ; 16      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_address[1]~0                                              ; 16      ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_grant_vector[1]~0                                         ; 16      ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1]                                                                                                               ; 16      ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                    ; 15      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|delayed_unxsync_rxdxx1                                                                                                                           ; 15      ;
; spi_touch:the_spi_touch|data_to_cpu[6]~1                                                                                                                                                               ; 15      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[31]                                                                                              ; 15      ;
; cpu:the_cpu|D_src2[26]~0                                                                                                                                                                               ; 15      ;
; cpu:the_cpu|D_iw[2]                                                                                                                                                                                    ; 15      ;
; cpu:the_cpu|D_iw[4]                                                                                                                                                                                    ; 15      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_a         ; 15      ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0]                                                                                                               ; 15      ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_waitrequest                                                                                                                             ; 15      ;
; cpu:the_cpu|i_read                                                                                                                                                                                     ; 15      ;
; cpu:the_cpu|A_mem_baddr[26]                                                                                                                                                                            ; 15      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|Equal0~3                                                                                                                                         ; 14      ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~59                                                                                                                         ; 14      ;
; jtag_uart_0:the_jtag_uart_0|wr_rfifo                                                                                                                                                                   ; 14      ;
; cpu:the_cpu|D_ic_fill_starting_d1                                                                                                                                                                      ; 14      ;
; cpu:the_cpu|ic_fill_line[5]                                                                                                                                                                            ; 14      ;
; cpu:the_cpu|A_mem_baddr[8]                                                                                                                                                                             ; 14      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|slowcount[0]                                                                           ; 14      ;
; spi_sdcard:the_spi_sdcard|transmitting                                                                                                                                                                 ; 14      ;
; sdram_0:the_sdram_0|m_addr[1]~4                                                                                                                                                                        ; 13      ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|always4~0                                                                                                                                        ; 13      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[20]                      ; 13      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[21]                      ; 13      ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|do_load_shifter                                                                                                                                  ; 13      ;
; spi_lcd22:the_spi_lcd22|Equal0~1                                                                                                                                                                       ; 13      ;
; cpu:the_cpu|hbreak_enabled                                                                                                                                                                             ; 13      ;
; cpu:the_cpu|D_iw[1]                                                                                                                                                                                    ; 13      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0       ; 13      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[37]                      ; 13      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[11]~15                          ; 13      ;
; sdram_0:the_sdram_0|m_state.100000000                                                                                                                                                                  ; 13      ;
; sdram_0:the_sdram_0|m_addr[1]~2                                                                                                                                                                        ; 13      ;
; cpu:the_cpu|A_mem_baddr[10]                                                                                                                                                                            ; 13      ;
; spi_lcd22:the_spi_lcd22|transmitting                                                                                                                                                                   ; 13      ;
; sld_hub:auto_hub|irsr_reg[6]                                                                                                                                                                           ; 12      ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                   ; 12      ;
; spi_lcd22:the_spi_lcd22|Equal0~2                                                                                                                                                                       ; 12      ;
; cpu:the_cpu|A_slow_inst_result[6]~25                                                                                                                                                                   ; 12      ;
; cpu:the_cpu|A_slow_inst_result[6]~24                                                                                                                                                                   ; 12      ;
; cpu:the_cpu|A_st_data[15]                                                                                                                                                                              ; 12      ;
; cpu:the_cpu|A_st_data[14]                                                                                                                                                                              ; 12      ;
; cpu:the_cpu|A_st_data[13]                                                                                                                                                                              ; 12      ;
; cpu:the_cpu|A_st_data[12]                                                                                                                                                                              ; 12      ;
; cpu:the_cpu|A_st_data[11]                                                                                                                                                                              ; 12      ;
; cpu:the_cpu|D_src2_imm[26]~4                                                                                                                                                                           ; 12      ;
; cpu:the_cpu|D_iw[0]                                                                                                                                                                                    ; 12      ;
; cpu:the_cpu|D_iw[3]                                                                                                                                                                                    ; 12      ;
; cpu:the_cpu|D_iw[5]                                                                                                                                                                                    ; 12      ;
; sdram_0:the_sdram_0|i_state.011                                                                                                                                                                        ; 12      ;
; sdram_0:the_sdram_0|i_state.000                                                                                                                                                                        ; 12      ;
; cpu:the_cpu|M_valid_from_E                                                                                                                                                                             ; 12      ;
; spi_lcd22:the_spi_lcd22|Equal2~0                                                                                                                                                                       ; 12      ;
; sdram_0:the_sdram_0|m_state.000001000                                                                                                                                                                  ; 12      ;
; spi_touch:the_spi_touch|transmitting                                                                                                                                                                   ; 12      ;
; spi_sdcard:the_spi_sdcard|SCLK_reg                                                                                                                                                                     ; 12      ;
; spi_lcd22:the_spi_lcd22|SCLK_reg                                                                                                                                                                       ; 12      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|SCLK_reg                                                                               ; 12      ;
; cpu:the_cpu|E_src2[4]                                                                                                                                                                                  ; 12      ;
; cpu:the_cpu|E_src2[0]                                                                                                                                                                                  ; 12      ;
; cpu:the_cpu|E_src2[1]                                                                                                                                                                                  ; 12      ;
; cpu:the_cpu|E_src2[2]                                                                                                                                                                                  ; 12      ;
; cpu:the_cpu|E_src2[3]                                                                                                                                                                                  ; 12      ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                    ; 11      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|do_start_rx                                                                                                                                      ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[24]                      ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[23]                      ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[18]                      ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[19]                      ; 11      ;
; jtag_uart_0:the_jtag_uart_0|r_val~0                                                                                                                                                                    ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[25]                      ; 11      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[26]                      ; 11      ;
; cpu:the_cpu|D_iw[8]                                                                                                                                                                                    ; 11      ;
; pd_s1_arbitrator:the_pd_s1|cpu_data_master_requests_pd_s1                                                                                                                                              ; 11      ;
; pc_s1_arbitrator:the_pc_s1|cpu_data_master_requests_pc_s1                                                                                                                                              ; 11      ;
; jtag_uart_0:the_jtag_uart_0|rvalid~0                                                                                                                                                                   ; 11      ;
; cpu:the_cpu|i_readdatavalid_d1                                                                                                                                                                         ; 11      ;
; sdram_0:the_sdram_0|Equal0~3                                                                                                                                                                           ; 11      ;
; sdram_0:the_sdram_0|i_state.101                                                                                                                                                                        ; 11      ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]                                                                                                                   ; 11      ;
; spi_sdcard:the_spi_sdcard|transmitting~3                                                                                                                                                               ; 11      ;
; spi_lcd22:the_spi_lcd22|transmitting~3                                                                                                                                                                 ; 11      ;
; sdram_0:the_sdram_0|m_state.000000100                                                                                                                                                                  ; 11      ;
; sdram_0:the_sdram_0|i_addr[12]                                                                                                                                                                         ; 11      ;
; lcd_cs:the_lcd_cs|data_out~0                                                                                                                                                                           ; 11      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|transmitting~0                                                                         ; 11      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|transmitting                                                                           ; 11      ;
; sld_hub:auto_hub|irf_reg[2][0]                                                                                                                                                                         ; 10      ;
; sld_hub:auto_hub|irsr_reg[1]                                                                                                                                                                           ; 10      ;
; sld_hub:auto_hub|irsr_reg[2]                                                                                                                                                                           ; 10      ;
; sld_hub:auto_hub|irsr_reg[0]                                                                                                                                                                           ; 10      ;
; spi_touch:the_spi_touch|transmitting~8                                                                                                                                                                 ; 10      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]~0                                                                                         ; 10      ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|got_new_char                                                                                                                                     ; 10      ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[6]~0                                                                       ; 10      ;
; cpu:the_cpu|ic_fill_dp_offset_nxt[2]~2                                                                                                                                                                 ; 10      ;
; cpu:the_cpu|ic_fill_dp_offset_nxt[1]~0                                                                                                                                                                 ; 10      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[34]                      ; 10      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[22]                      ; 10      ;
; uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs|control_wr_strobe~0                                                                                                                          ; 10      ;
; sdram_0:the_sdram_0|i_state.010                                                                                                                                                                        ; 10      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1|always15~0                                             ; 10      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[3]                                                                                                           ; 10      ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[2]                                                                                                           ; 10      ;
; sld_hub:auto_hub|irsr_reg[5]                                                                                                                                                                           ; 9       ;
; ~GND                                                                                                                                                                                                   ; 9       ;
; cpu:the_cpu|ic_tag_clr_valid_bits_nxt                                                                                                                                                                  ; 9       ;
; spi_touch:the_spi_touch|data_to_cpu[1]~2                                                                                                                                                               ; 9       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~62                                                                                                                         ; 9       ;
; pb_s1_arbitrator:the_pb_s1|cpu_data_master_requests_pb_s1                                                                                                                                              ; 9       ;
; pa_s1_arbitrator:the_pa_s1|cpu_data_master_requests_pa_s1                                                                                                                                              ; 9       ;
; cpu:the_cpu|A_ld_align_sh16                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[17]                      ; 9       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[27]                      ; 9       ;
; cpu:the_cpu|ic_fill_dp_offset_nxt[0]~3                                                                                                                                                                 ; 9       ;
; cpu:the_cpu|M_alu_result[0]                                                                                                                                                                            ; 9       ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~1                                                                                  ; 9       ;
; cpu:the_cpu|E_iw[0]                                                                                                                                                                                    ; 9       ;
; cpu:the_cpu|E_iw[3]                                                                                                                                                                                    ; 9       ;
; cpu:the_cpu|E_iw[1]                                                                                                                                                                                    ; 9       ;
; spi_lcd22:the_spi_lcd22|Equal0~0                                                                                                                                                                       ; 9       ;
; cpu:the_cpu|ic_fill_line[4]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|ic_fill_line[3]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|ic_fill_line[2]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|ic_fill_line[1]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|ic_fill_line[0]                                                                                                                                                                            ; 9       ;
; sdram_0:the_sdram_0|m_count[1]                                                                                                                                                                         ; 9       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_data_master_qualified_request_sdram_0_s1~3                                                                                                                    ; 9       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state                                                                                                                      ; 9       ;
; spi_touch:the_spi_touch|shift_reg[4]~2                                                                                                                                                                 ; 9       ;
; sdram_0:the_sdram_0|m_state.010000000                                                                                                                                                                  ; 9       ;
; cpu:the_cpu|A_mem_baddr[11]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|A_mem_baddr[12]                                                                                                                                                                            ; 9       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[4]                                                                                                           ; 9       ;
; ~QIC_CREATED_GND~I                                                                                                                                                                                     ; 8       ;
; sld_hub:auto_hub|irsr_reg[4]                                                                                                                                                                           ; 8       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                                               ; 8       ;
; spi_touch:the_spi_touch|shift_reg[4]~11                                                                                                                                                                ; 8       ;
; spi_sdcard:the_spi_sdcard|shift_reg[0]~10                                                                                                                                                              ; 8       ;
; spi_lcd22:the_spi_lcd22|shift_reg[0]~10                                                                                                                                                                ; 8       ;
; cpu:the_cpu|M_br_cond_taken_history[0]~0                                                                                                                                                               ; 8       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write~0                                                                                                               ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[16]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[15]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[14]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[12]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[13]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[11]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[10]                      ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[8]                       ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[9]                       ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[6]                       ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[7]                       ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[69]~2                                                                                                    ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[5]                       ; 8       ;
; cpu:the_cpu|A_ld_align_byte1_fill                                                                                                                                                                      ; 8       ;
; cpu:the_cpu|A_rot_pass1                                                                                                                                                                                ; 8       ;
; cpu:the_cpu|A_rot_sel_fill1                                                                                                                                                                            ; 8       ;
; cpu:the_cpu|A_rot_pass2                                                                                                                                                                                ; 8       ;
; cpu:the_cpu|A_rot_sel_fill2                                                                                                                                                                            ; 8       ;
; cpu:the_cpu|A_rot_pass3                                                                                                                                                                                ; 8       ;
; cpu:the_cpu|A_rot_sel_fill3                                                                                                                                                                            ; 8       ;
; cpu:the_cpu|ic_fill_valid_bits_en                                                                                                                                                                      ; 8       ;
; sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave                                                                                                     ; 8       ;
; cpu:the_cpu|A_rot_pass0                                                                                                                                                                                ; 8       ;
; cpu:the_cpu|A_rot_sel_fill0                                                                                                                                                                            ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[4]                       ; 8       ;
; uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs|tx_wr_strobe~0                                                                                                                               ; 8       ;
; pd:the_pd|always2~0                                                                                                                                                                                    ; 8       ;
; pd:the_pd|always1~0                                                                                                                                                                                    ; 8       ;
; pc:the_pc|always2~0                                                                                                                                                                                    ; 8       ;
; pc:the_pc|always1~0                                                                                                                                                                                    ; 8       ;
; pb:the_pb|always2~0                                                                                                                                                                                    ; 8       ;
; pb:the_pb|always1~0                                                                                                                                                                                    ; 8       ;
; pa:the_pa|always2~0                                                                                                                                                                                    ; 8       ;
; pa:the_pa|always1~0                                                                                                                                                                                    ; 8       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[3]                       ; 8       ;
; cpu:the_cpu|Equal259~0                                                                                                                                                                                 ; 8       ;
; cpu:the_cpu|ic_fill_dp_offset[0]                                                                                                                                                                       ; 8       ;
; spi_touch:the_spi_touch|write_tx_holding                                                                                                                                                               ; 8       ;
; spi_sdcard:the_spi_sdcard|write_tx_holding                                                                                                                                                             ; 8       ;
; spi_lcd22:the_spi_lcd22|write_tx_holding                                                                                                                                                               ; 8       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|write_tx_holding                                                                       ; 8       ;
; cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~4                                                                                                              ; 8       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_instruction_master_qualified_request_sdram_0_s1~0                                                                                                             ; 8       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module                                                                              ; 8       ;
; spi_touch:the_spi_touch|control_wr_strobe                                                                                                                                                              ; 8       ;
; spi_sdcard:the_spi_sdcard|control_wr_strobe                                                                                                                                                            ; 8       ;
; spi_lcd22:the_spi_lcd22|control_wr_strobe                                                                                                                                                              ; 8       ;
; sdram_0:the_sdram_0|pending                                                                                                                                                                            ; 8       ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|Equal1~0                                                                                                                 ; 8       ;
; cpu:the_cpu|A_mem_baddr[9]                                                                                                                                                                             ; 8       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|shift_reg[1]~1                                                                         ; 8       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|control_wr_strobe                                                                      ; 8       ;
; cpu:the_cpu|ic_fill_line[6]                                                                                                                                                                            ; 8       ;
; cpu:the_cpu|ic_fill_tag[0]                                                                                                                                                                             ; 8       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_data_master_requests_sdram_0_s1~0                                                                                                                             ; 8       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[1]                                                                                             ; 8       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[2]                                                                                             ; 8       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[0]                                                                                             ; 8       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                                               ; 7       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                                                               ; 7       ;
; uart_9600_s1_arbitrator:the_uart_9600_s1|cpu_data_master_granted_uart_9600_s1~4                                                                                                                        ; 7       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]                                                                                           ; 7       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[6]~1                                                                       ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0                                                                              ; 7       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|b_full                                  ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk1[69]~2                                                                                                    ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[2]                       ; 7       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~57                                                                                                                         ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[1]                       ; 7       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|always1~0                                                            ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[4]~65                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[5]~63                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[6]~61                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[7]~59                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[8]~57                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[9]~55                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[10]~53                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[11]~51                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[12]~49                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[13]~47                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[14]~45                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[15]~43                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[16]~41                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[17]~39                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[18]~37                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[19]~35                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[20]~33                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[21]~31                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[22]~29                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[23]~27                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[24]~25                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[25]~23                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[26]~21                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[27]~19                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[28]~17                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[29]~15                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[30]~13                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[31]~11                                                                                                                                                                ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[0]~9                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|D_iw[7]                                                                                                                                                                                    ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[1]~7                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[2]~5                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|A_wr_data_unfiltered[3]~3                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~0                                                                                                             ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[33]                      ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[0]                       ; 7       ;
; sdram_0:the_sdram_0|i_count[1]                                                                                                                                                                         ; 7       ;
; cpu:the_cpu|E_src1[4]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[5]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[6]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[7]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[8]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[9]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[10]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[11]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[12]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[13]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[14]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[15]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[16]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[17]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[18]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[19]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[20]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[21]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[22]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[23]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[24]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[25]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|E_src1[26]                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|ic_tag_clr_valid_bits_nxt~2                                                                                                                                                                ; 7       ;
; cpu:the_cpu|Equal171~0                                                                                                                                                                                 ; 7       ;
; cpu:the_cpu|F_pc[0]                                                                                                                                                                                    ; 7       ;
; cpu:the_cpu|F_pc[1]                                                                                                                                                                                    ; 7       ;
; cpu:the_cpu|E_src1[2]                                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|E_src1[3]                                                                                                                                                                                  ; 7       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|b_full                                  ; 7       ;
; sdram_0:the_sdram_0|comb~0                                                                                                                                                                             ; 7       ;
; jtag_uart_0:the_jtag_uart_0|always2~0                                                                                                                                                                  ; 7       ;
; cpu:the_cpu|ic_fill_ap_offset[1]~0                                                                                                                                                                     ; 7       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|virtual_state_cdr                         ; 7       ;
; spi_touch:the_spi_touch|tx_holding_primed                                                                                                                                                              ; 7       ;
; spi_sdcard:the_spi_sdcard|tx_holding_primed                                                                                                                                                            ; 7       ;
; spi_lcd22:the_spi_lcd22|tx_holding_primed                                                                                                                                                              ; 7       ;
; sdram_0:the_sdram_0|m_state.000100000                                                                                                                                                                  ; 7       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|tx_holding_primed                                                                      ; 7       ;
; nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|data_out                                                                                                        ; 7       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|state[4]                                                                               ; 7       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|state[0]                                                                               ; 7       ;
; sld_hub:auto_hub|node_ena_proc~1                                                                                                                                                                       ; 6       ;
; sld_hub:auto_hub|node_ena[1]~reg0                                                                                                                                                                      ; 6       ;
; sld_hub:auto_hub|irsr_reg[3]                                                                                                                                                                           ; 6       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|_~4                                     ; 6       ;
; sdram_0:the_sdram_0|m_next~21                                                                                                                                                                          ; 6       ;
; cpu:the_cpu|E_ctrl_shift_rot_left                                                                                                                                                                      ; 6       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|_~0                                     ; 6       ;
; cpu:the_cpu|A_ienable_reg_irq0~0                                                                                                                                                                       ; 6       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[0] ; 6       ;
; cpu:the_cpu|ic_tag_wraddress[1]~6                                                                                                                                                                      ; 6       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~1                                                                                                          ; 6       ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|tx_ready                                                                                                                                         ; 6       ;
; cpu:the_cpu|D_ctrl_unsigned_lo_imm16                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state                                                                                                  ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~29                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~25                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~21                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~17                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~13                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~9                                                                                                                                                                  ; 6       ;
; cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~5                                                                                                                                                                  ; 6       ;
; cpu:the_cpu|Equal171~2                                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|D_iw[6]                                                                                                                                                                                    ; 6       ;
; cpu:the_cpu|M_alu_result[1]                                                                                                                                                                            ; 6       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~reg0                                                                                                                 ; 6       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[0] ; 6       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                             ; 6       ;
; cpu:the_cpu|E_src1[31]                                                                                                                                                                                 ; 6       ;
; cpu:the_cpu|E_iw[2]                                                                                                                                                                                    ; 6       ;
; cpu:the_cpu|latched_oci_tb_hbreak_req                                                                                                                                                                  ; 6       ;
; cpu:the_cpu|ic_fill_dp_offset[1]                                                                                                                                                                       ; 6       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[0]~0                                                                                                                      ; 6       ;
; cpu:the_cpu|D_issue                                                                                                                                                                                    ; 6       ;
; cpu:the_cpu|always88~0                                                                                                                                                                                 ; 6       ;
; sdram_0:the_sdram_0|pending~10                                                                                                                                                                         ; 6       ;
; cpu:the_cpu|M_alu_result[5]                                                                                                                                                                            ; 6       ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|Equal0~0                                                                                                                 ; 6       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]                                                                                                                                          ; 6       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[1]                                                                                                                                          ; 6       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_qualified_request_cpu_jtag_debug_module~1                                                                                   ; 6       ;
; spi_touch:the_spi_touch|always11~0                                                                                                                                                                     ; 6       ;
; spi_touch:the_spi_touch|wr_strobe                                                                                                                                                                      ; 6       ;
; spi_sdcard:the_spi_sdcard|always11~0                                                                                                                                                                   ; 6       ;
; spi_sdcard:the_spi_sdcard|wr_strobe                                                                                                                                                                    ; 6       ;
; spi_sdcard:the_spi_sdcard|state[4]                                                                                                                                                                     ; 6       ;
; spi_sdcard:the_spi_sdcard|state[0]                                                                                                                                                                     ; 6       ;
; spi_lcd22:the_spi_lcd22|always11~0                                                                                                                                                                     ; 6       ;
; spi_lcd22:the_spi_lcd22|wr_strobe                                                                                                                                                                      ; 6       ;
; spi_lcd22:the_spi_lcd22|state[4]                                                                                                                                                                       ; 6       ;
; spi_lcd22:the_spi_lcd22|state[0]                                                                                                                                                                       ; 6       ;
; pd_s1_arbitrator:the_pd_s1|cpu_data_master_requests_pd_s1~0                                                                                                                                            ; 6       ;
; touch_irq_s1_arbitrator:the_touch_irq_s1|cpu_data_master_granted_touch_irq_s1~0                                                                                                                        ; 6       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|always11~0                                                                             ; 6       ;
; cpu:the_cpu|ic_fill_ap_offset[2]                                                                                                                                                                       ; 6       ;
; cpu:the_cpu|ic_fill_ap_offset[0]                                                                                                                                                                       ; 6       ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_arb_addend[0]                                             ; 6       ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_arb_addend[1]                                             ; 6       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~3                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[13]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[14]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[15]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[16]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[17]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[18]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[19]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[20]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[21]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[22]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[23]                                                                                                                                                                            ; 6       ;
; cpu:the_cpu|A_mem_baddr[24]                                                                                                                                                                            ; 6       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|Equal9~0                                                                               ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[26]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[23]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[24]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[25]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[27]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[28]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[29]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[30]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[31]                                                                                            ; 6       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|q_b[22]                                                                                            ; 6       ;
; cpu:the_cpu|F_pc[24]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[23]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[22]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[21]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[20]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[19]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[18]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[17]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[16]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[15]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[14]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[13]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[12]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[11]                                                                                                                                                                                   ; 6       ;
; cpu:the_cpu|F_pc[10]                                                                                                                                                                                   ; 6       ;
; spi_touch:the_spi_touch|slowcount[5]                                                                                                                                                                   ; 6       ;
; spi_touch:the_spi_touch|slowcount[4]                                                                                                                                                                   ; 6       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]~19                                                                                                                                            ; 5       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]~10                                                                                                                                            ; 5       ;
; sld_hub:auto_hub|shadow_irf_reg[2][0]~9                                                                                                                                                                ; 5       ;
; sld_hub:auto_hub|shadow_irf_reg[1][0]~2                                                                                                                                                                ; 5       ;
; sld_hub:auto_hub|irsr_reg[2]~3                                                                                                                                                                         ; 5       ;
; sld_hub:auto_hub|irsr_reg[2]~0                                                                                                                                                                         ; 5       ;
; sld_hub:auto_hub|irf_reg[2][0]~12                                                                                                                                                                      ; 5       ;
; sld_hub:auto_hub|irf_reg[1][0]~5                                                                                                                                                                       ; 5       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                                               ; 5       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                                               ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1|updated_one_count~4                                    ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_5                                                               ; 5       ;
; cpu:the_cpu|D_control_reg_rddata_muxed[2]~0                                                                                                                                                            ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_4                                                               ; 5       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[11]~2                                                                      ; 5       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|ROE                                                                                    ; 5       ;
; spi_touch:the_spi_touch|ROE                                                                                                                                                                            ; 5       ;
; spi_lcd22:the_spi_lcd22|ROE                                                                                                                                                                            ; 5       ;
; spi_sdcard:the_spi_sdcard|ROE                                                                                                                                                                          ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[3] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[4] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[5] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[1] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[2] ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[31]                      ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[30]                      ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[29]                      ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_3                                                               ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal1~0                                                                                                     ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|xbrk_ctrl1[0]~0                                                                                                ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|xbrk_ctrl0[0]~0                                                                                                ; 5       ;
; cpu:the_cpu|M_iw[6]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|Equal154~5                                                                                                                                                                                 ; 5       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~20                                                                                                                          ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~2                                                                                                                                              ; 5       ;
; cpu:the_cpu|clr_break_line                                                                                                                                                                             ; 5       ;
; cpu:the_cpu|A_mem_baddr[0]                                                                                                                                                                             ; 5       ;
; cpu:the_cpu|A_mem_baddr[1]                                                                                                                                                                             ; 5       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|jdo[28]                      ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_2                                                               ; 5       ;
; cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~11                                                                                                                                                                ; 5       ;
; cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~7                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|D_iw[19]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|D_iw[20]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|D_iw[18]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|A_status_reg_pie                                                                                                                                                                           ; 5       ;
; cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~3                                                                                                                                                                 ; 5       ;
; DS18B20:the_DS18B20|always2~0                                                                                                                                                                          ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[1] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[2] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[3] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[4] ; 5       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw|counter_reg_bit[5] ; 5       ;
; sdram_0:the_sdram_0|i_count[2]                                                                                                                                                                         ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_1                                                               ; 5       ;
; cpu:the_cpu|E_src1[27]                                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|E_src1[28]                                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|E_src1[29]                                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|E_src1[30]                                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|E_iw[12]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|E_iw[14]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|E_iw[15]                                                                                                                                                                                   ; 5       ;
; cpu:the_cpu|E_valid_from_D                                                                                                                                                                             ; 5       ;
; cpu:the_cpu|ic_fill_dp_offset[2]                                                                                                                                                                       ; 5       ;
; cpu:the_cpu|F_pc[6]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[7]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[9]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[8]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[4]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[5]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[3]                                                                                                                                                                                    ; 5       ;
; cpu:the_cpu|F_pc[2]                                                                                                                                                                                    ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|updated_one_count~0                                                  ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_winner~0                                                                                                                                           ; 5       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module~0                                                                                      ; 5       ;
; cpu:the_cpu|E_src1[0]                                                                                                                                                                                  ; 5       ;
; cpu:the_cpu|E_src1[1]                                                                                                                                                                                  ; 5       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0                                                                                                                  ; 5       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~6                                                                                                                 ; 5       ;
; spi_touch:the_spi_touch|p1_slowcount~1                                                                                                                                                                 ; 5       ;
; cpu:the_cpu|M_alu_result[7]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[8]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[9]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[10]                                                                                                                                                                           ; 5       ;
; cpu:the_cpu|M_alu_result[6]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[4]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[2]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|M_alu_result[11]                                                                                                                                                                           ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_instruction_master_requests_sdram_0_s1~0                                                                                                                      ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable                                                                                                                                 ; 5       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]                                                                                                         ; 5       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]                                                                                                         ; 5       ;
; cpu:the_cpu|A_mem_stall                                                                                                                                                                                ; 5       ;
; cpu:the_cpu|A_shift_rot_stall                                                                                                                                                                          ; 5       ;
; cpu:the_cpu|M_alu_result[3]                                                                                                                                                                            ; 5       ;
; DS18B20_s1_arbitrator:the_DS18B20_s1|cpu_data_master_requests_DS18B20_s1~4                                                                                                                             ; 5       ;
; spi_touch:the_spi_touch|state[4]                                                                                                                                                                       ; 5       ;
; spi_touch:the_spi_touch|state[0]                                                                                                                                                                       ; 5       ;
; spi_touch:the_spi_touch|Equal2~0                                                                                                                                                                       ; 5       ;
; spi_sdcard:the_spi_sdcard|Equal9~0                                                                                                                                                                     ; 5       ;
; spi_sdcard:the_spi_sdcard|slowcount[0]                                                                                                                                                                 ; 5       ;
; spi_lcd22:the_spi_lcd22|Equal9~0                                                                                                                                                                       ; 5       ;
; spi_lcd22:the_spi_lcd22|slowcount[0]                                                                                                                                                                   ; 5       ;
; spi_lcd22:the_spi_lcd22|slowcount[1]                                                                                                                                                                   ; 5       ;
; sdram_0:the_sdram_0|active_cs_n                                                                                                                                                                        ; 5       ;
; jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_0_avalon_jtag_slave~0                                                                    ; 5       ;
; pb_s1_arbitrator:the_pb_s1|cpu_data_master_requests_pb_s1~0                                                                                                                                            ; 5       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~4                                                                                     ; 5       ;
; cpu:the_cpu|ic_fill_tag[14]                                                                                                                                                                            ; 5       ;
; cpu:the_cpu|ic_fill_ap_offset[1]                                                                                                                                                                       ; 5       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|wr_strobe                                                                              ; 5       ;
; cpu:the_cpu|lpm_add_sub:Add10|add_sub_hui:auto_generated|result_int[2]~4                                                                                                                               ; 5       ;
; cpu:the_cpu|lpm_add_sub:Add10|add_sub_hui:auto_generated|result_int[1]~2                                                                                                                               ; 5       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                                                                                ; 5       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]~7                                                                                                                                                  ; 4       ;
; sld_hub:auto_hub|node_ena_proc~0                                                                                                                                                                       ; 4       ;
; sld_hub:auto_hub|irf_proc~0                                                                                                                                                                            ; 4       ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                                                   ; 4       ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                    ; 4       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_end_xfer~2                                                                                                                                             ; 4       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_0_s1|full_6                                                               ; 4       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|status_wr_strobe                                                                       ; 4       ;
; spi_touch:the_spi_touch|status_wr_strobe                                                                                                                                                               ; 4       ;
; uart_9600:the_uart_9600|uart_9600_regs:the_uart_9600_regs|status_wr_strobe~0                                                                                                                           ; 4       ;
; spi_lcd22:the_spi_lcd22|status_wr_strobe                                                                                                                                                               ; 4       ;
; spi_sdcard:the_spi_sdcard|status_wr_strobe                                                                                                                                                             ; 4       ;
; cpu:the_cpu|E_ctrl_rot                                                                                                                                                                                 ; 4       ;
; sdram_0:the_sdram_0|za_data[1]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[2]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[3]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[4]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[5]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[0]                                                                                                                                                                         ; 4       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|RRDY                                                                                   ; 4       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|TOE                                                                                    ; 4       ;
; spi_sdcard:the_spi_sdcard|RRDY                                                                                                                                                                         ; 4       ;
; spi_sdcard:the_spi_sdcard|TOE                                                                                                                                                                          ; 4       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|rx_char_ready                                                                                                                                    ; 4       ;
; uart_9600:the_uart_9600|uart_9600_tx:the_uart_9600_tx|tx_overrun                                                                                                                                       ; 4       ;
; spi_lcd22:the_spi_lcd22|RRDY                                                                                                                                                                           ; 4       ;
; spi_lcd22:the_spi_lcd22|TOE                                                                                                                                                                            ; 4       ;
; spi_touch:the_spi_touch|RRDY                                                                                                                                                                           ; 4       ;
; spi_touch:the_spi_touch|TOE                                                                                                                                                                            ; 4       ;
; sdram_0:the_sdram_0|za_data[10]                                                                                                                                                                        ; 4       ;
; sdram_0:the_sdram_0|za_data[9]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[8]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[7]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[6]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|za_data[15]                                                                                                                                                                        ; 4       ;
; sdram_0:the_sdram_0|za_data[14]                                                                                                                                                                        ; 4       ;
; sdram_0:the_sdram_0|za_data[13]                                                                                                                                                                        ; 4       ;
; sdram_0:the_sdram_0|za_data[12]                                                                                                                                                                        ; 4       ;
; sdram_0:the_sdram_0|za_data[11]                                                                                                                                                                        ; 4       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|framing_error                                                                                                                                    ; 4       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|break_detect                                                                                                                                     ; 4       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|rx_overrun                                                                                                                                       ; 4       ;
; cpu:the_cpu|A_rot_mask[4]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_rot_mask[5]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_rot_mask[6]                                                                                                                                                                              ; 4       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~55                                                                                                                          ; 4       ;
; cpu:the_cpu|A_rot_mask[7]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|M_ctrl_crst                                                                                                                                                                                ; 4       ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|ram_block1a0~0                                                                                     ; 4       ;
; cpu:the_cpu|A_rot_mask[0]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_rot_mask[1]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_rot_mask[2]                                                                                                                                                                              ; 4       ;
; touch_irq_s1_arbitrator:the_touch_irq_s1|cpu_data_master_granted_touch_irq_s1                                                                                                                          ; 4       ;
; touch_irq_s1_arbitrator:the_touch_irq_s1|cpu_data_master_granted_touch_irq_s1~1                                                                                                                        ; 4       ;
; cpu:the_cpu|A_rot_mask[3]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_dst_regnum_from_M[4]                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|A_dst_regnum_from_M[3]                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|A_dst_regnum_from_M[2]                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|A_dst_regnum_from_M[1]                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|A_dst_regnum_from_M[0]                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|A_wr_dst_reg_from_M                                                                                                                                                                        ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~1                                                                                                     ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~0                                                                                                     ; 4       ;
; cpu:the_cpu|A_st_data[31]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[30]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[29]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[28]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[27]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[26]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[25]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[24]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[23]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[22]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[21]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[20]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[19]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[18]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[17]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_st_data[16]                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|A_mem_baddr[25]                                                                                                                                                                            ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always2~0                                                                                                      ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|always4~0                                                                                                      ; 4       ;
; sdram_0:the_sdram_0|i_count[0]                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|i_refs[0]                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|M_alu_result[25]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_single_step_mode                                                                                         ; 4       ;
; cpu:the_cpu|ic_fill_dp_offset_en~0                                                                                                                                                                     ; 4       ;
; cpu:the_cpu|F_iw[4]~10                                                                                                                                                                                 ; 4       ;
; cpu:the_cpu|D_dst_regnum[0]~6                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|D_iw[17]                                                                                                                                                                                   ; 4       ;
; cpu:the_cpu|D_dst_regnum[2]~5                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|D_dst_regnum[3]~4                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|D_dst_regnum[4]~3                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|D_dst_regnum[4]~2                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|D_dst_regnum[1]~1                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|Equal154~2                                                                                                                                                                                 ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1                                                                                                                ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled~1                                                                                                            ; 4       ;
; sdram_0:the_sdram_0|i_count[0]~0                                                                                                                                                                       ; 4       ;
; nios_clock_0:the_nios_clock_0|nios_clock_0_slave_FSM:slave_FSM|Selector1~0                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_ap_cnt[0]                                                                                                                                                                          ; 4       ;
; cpu:the_cpu|E_br_result~0                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|E_ctrl_br_cond                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|E_iw[11]                                                                                                                                                                                   ; 4       ;
; cpu:the_cpu|E_iw[13]                                                                                                                                                                                   ; 4       ;
; cpu:the_cpu|E_iw[16]                                                                                                                                                                                   ; 4       ;
; cpu:the_cpu|Equal199~1                                                                                                                                                                                 ; 4       ;
; cpu:the_cpu|E_valid~2                                                                                                                                                                                  ; 4       ;
; cpu:the_cpu|M_ctrl_invalidate_i                                                                                                                                                                        ; 4       ;
; cpu:the_cpu|D_op_srli~0                                                                                                                                                                                ; 4       ;
; cpu:the_cpu|D_ctrl_shift_right_arith~0                                                                                                                                                                 ; 4       ;
; cpu:the_cpu|A_mul_cnt[0]                                                                                                                                                                               ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10]                                                                                                               ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled                                                                                                              ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|ir[0]                        ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|enable_action_strobe         ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|ir[1]                        ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|virtual_state_uir~0                       ; 4       ;
; sdram_0:the_sdram_0|i_state.111                                                                                                                                                                        ; 4       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|in_a_write_cycle                                                                                                                                                  ; 4       ;
; sdram_0:the_sdram_0|Selector25~5                                                                                                                                                                       ; 4       ;
; nios_clock_0:the_nios_clock_0|nios_clock_0_slave_FSM:slave_FSM|slave_state.010                                                                                                                         ; 4       ;
; nios_clock_0:the_nios_clock_0|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                              ; 4       ;
; cpu:the_cpu|D_pc[2]                                                                                                                                                                                    ; 4       ;
; cpu:the_cpu|D_pc[0]                                                                                                                                                                                    ; 4       ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|WideOr1                                                                                             ; 4       ;
; cpu:the_cpu|M_alu_result[13]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[14]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[15]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[16]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[17]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[18]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[19]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[20]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[21]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[22]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[23]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[24]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[26]                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_alu_result[12]                                                                                                                                                                           ; 4       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|last_cycle_cpu_data_master_granted_slave_sdram_0_s1                                                                                                               ; 4       ;
; cpu:the_cpu|A_mem_byte_en[3]                                                                                                                                                                           ; 4       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module                                                                                        ; 4       ;
; cpu:the_cpu|D_pc[1]                                                                                                                                                                                    ; 4       ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|cpu_instruction_master_granted_epcs_flash_controller_0_epcs_control_port~0                          ; 4       ;
; nios_clock_0:the_nios_clock_0|master_address[3]                                                                                                                                                        ; 4       ;
; nios_clock_0:the_nios_clock_0|master_address[2]                                                                                                                                                        ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1]                                                                                                                   ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid                                                                                                            ; 4       ;
; jtag_uart_0:the_jtag_uart_0|t_dav                                                                                                                                                                      ; 4       ;
; spi_touch:the_spi_touch|Equal9~1                                                                                                                                                                       ; 4       ;
; spi_touch:the_spi_touch|Equal9~0                                                                                                                                                                       ; 4       ;
; spi_sdcard:the_spi_sdcard|slowcount[1]                                                                                                                                                                 ; 4       ;
; spi_lcd22:the_spi_lcd22|slowcount[2]                                                                                                                                                                   ; 4       ;
; sdram_0:the_sdram_0|WideOr16~0                                                                                                                                                                         ; 4       ;
; sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[42]~1                                                                                                            ; 4       ;
; sdram_0:the_sdram_0|f_pop                                                                                                                                                                              ; 4       ;
; cpu:the_cpu|ic_fill_tag[1]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[2]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[3]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[4]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[5]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[6]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[7]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[8]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[9]                                                                                                                                                                             ; 4       ;
; cpu:the_cpu|ic_fill_tag[10]                                                                                                                                                                            ; 4       ;
; cpu:the_cpu|ic_fill_tag[11]                                                                                                                                                                            ; 4       ;
; cpu:the_cpu|ic_fill_tag[12]                                                                                                                                                                            ; 4       ;
; spi_touch:the_spi_touch|SCLK_reg                                                                                                                                                                       ; 4       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[31]                             ; 4       ;
; cpu:the_cpu|M_regnum_b_cmp_D                                                                                                                                                                           ; 4       ;
; cpu:the_cpu|M_regnum_a_cmp_D                                                                                                                                                                           ; 4       ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                  ; 3       ;
; sld_hub:auto_hub|reset_ena_reg_proc~0                                                                                                                                                                  ; 3       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|clear_signal                                                                                                                                                  ; 3       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR~5                                                                                                                                                     ; 3       ;
; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR~3                                                                                                                                                     ; 3       ;
; sld_hub:auto_hub|hub_mode_reg[0]                                                                                                                                                                       ; 3       ;
; sld_hub:auto_hub|virtual_ir_dr_scan_proc~0                                                                                                                                                             ; 3       ;
; sld_hub:auto_hub|jtag_ir_reg[1]                                                                                                                                                                        ; 3       ;
; sld_hub:auto_hub|virtual_dr_scan_reg                                                                                                                                                                   ; 3       ;
; sld_hub:auto_hub|irf_reg[2][0]~11                                                                                                                                                                      ; 3       ;
; sld_hub:auto_hub|irf_reg[1][0]~4                                                                                                                                                                       ; 3       ;
; sld_hub:auto_hub|Equal3~0                                                                                                                                                                              ; 3       ;
; sld_hub:auto_hub|Equal9~0                                                                                                                                                                              ; 3       ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|node_ena[2]~reg0                                                                                                                                                                      ; 3       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~181                                                                                                                         ; 3       ;
; DS18B20_s1_arbitrator:the_DS18B20_s1|cpu_data_master_requests_DS18B20_s1                                                                                                                               ; 3       ;
; sdram_0:the_sdram_0|m_next~22                                                                                                                                                                          ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]                                                                                           ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|delayed_unxrx_in_processxx3                                                                                                                      ; 3       ;
; uart_9600:the_uart_9600|uart_9600_rx:the_uart_9600_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]                                                                                           ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[4]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[4]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[4]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[4]                                                                                                                                                      ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[5]                                                                ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|rx_holding_reg[5]                                                                      ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[5]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[5]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|data_to_cpu[5]~2                                                                                                                                                             ; 3       ;
; spi_sdcard:the_spi_sdcard|data_to_cpu[5]~1                                                                                                                                                             ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[5]                                                                                                                                                      ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[6]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[6]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[6]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[6]                                                                                                                                                      ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[7]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[7]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[7]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[7]                                                                                                                                                      ; 3       ;
; jtag_uart_0:the_jtag_uart_0|ien_AE~0                                                                                                                                                                   ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|TRDY~0                                                                                 ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|EOP                                                                                    ; 3       ;
; spi_sdcard:the_spi_sdcard|TRDY~0                                                                                                                                                                       ; 3       ;
; spi_sdcard:the_spi_sdcard|EOP                                                                                                                                                                          ; 3       ;
; spi_lcd22:the_spi_lcd22|TRDY~0                                                                                                                                                                         ; 3       ;
; spi_lcd22:the_spi_lcd22|EOP                                                                                                                                                                            ; 3       ;
; spi_touch:the_spi_touch|TRDY~0                                                                                                                                                                         ; 3       ;
; spi_touch:the_spi_touch|EOP                                                                                                                                                                            ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[0]                                                                ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[0]                                                                                                                                                      ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[0]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[0]                                                                                                                                                        ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[1]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[1]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[1]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[1]                                                                                                                                                      ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[2]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[2]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[2]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[2]                                                                                                                                                      ; 3       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|endofpacketvalue_reg[3]                                                                ; 3       ;
; spi_touch:the_spi_touch|endofpacketvalue_reg[3]                                                                                                                                                        ; 3       ;
; spi_lcd22:the_spi_lcd22|endofpacketvalue_reg[3]                                                                                                                                                        ; 3       ;
; spi_sdcard:the_spi_sdcard|endofpacketvalue_reg[3]                                                                                                                                                      ; 3       ;
; cpu:the_cpu|M_ctrl_ld8                                                                                                                                                                                 ; 3       ;
; cpu:the_cpu|E_src2_reg[5]                                                                                                                                                                              ; 3       ;
; cpu:the_cpu|E_src2_reg[4]                                                                                                                                                                              ; 3       ;
; cpu:the_cpu|E_src2_reg[3]                                                                                                                                                                              ; 3       ;
; nios_clock_0:the_nios_clock_0|nios_clock_0_master_FSM:master_FSM|master_read                                                                                                                           ; 3       ;
; cpu:the_cpu|E_src2_reg[6]                                                                                                                                                                              ; 3       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~119                                                                                                                        ; 3       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~110                                                                                                                        ; 3       ;
; cpu:the_cpu|d_readdata_d1[23]                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|d_readdata_d1[31]                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|M_ctrl_exception                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|A_estatus_reg_pie                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|A_bstatus_reg_pie                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|M_wrctl_bstatus~0                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|M_iw[8]                                                                                                                                                                                    ; 3       ;
; cpu:the_cpu|M_ctrl_wrctl_inst                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|M_iw[7]                                                                                                                                                                                    ; 3       ;
; cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[0]                                                                                                                  ; 3       ;
; cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~19                                                                                                                          ; 3       ;
; cpu:the_cpu|M_dst_regnum[4]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|M_wr_dst_reg_from_E                                                                                                                                                                        ; 3       ;
; cpu:the_cpu|M_dst_regnum[2]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|M_dst_regnum[3]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|M_dst_regnum[0]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|M_dst_regnum[1]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_error                                                                                                  ; 3       ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                             ; 3       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~11                                                                                                                ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_ocireg~0                                                                                         ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk0[64]                                                                                                      ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[7]~8                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~7                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~6                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[4]~5                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[3]~4                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[2]~3                                                                                                          ; 3       ;
; cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~2                                                                                                          ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr                                                                                                                ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[36]                             ; 3       ;
; cpu:the_cpu|E_src2_reg[1]                                                                                                                                                                              ; 3       ;
; sdram_0:the_sdram_0|i_count[0]~1                                                                                                                                                                       ; 3       ;
; sdram_0:the_sdram_0|i_refs[1]                                                                                                                                                                          ; 3       ;
; sdram_0:the_sdram_0|i_refs[2]                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|E_src2_reg[7]                                                                                                                                                                              ; 3       ;
; cpu:the_cpu|E_alu_result[25]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_alu_result[27]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|E_alu_result[27]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_alu_result[28]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|E_alu_result[28]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_alu_result[29]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|E_alu_result[29]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_alu_result[30]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|E_alu_result[30]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|E_alu_result[31]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_alu_result[31]                                                                                                                                                                           ; 3       ;
; cpu:the_cpu|M_ctrl_break                                                                                                                                                                               ; 3       ;
; cpu:the_cpu|M_op_eret~3                                                                                                                                                                                ; 3       ;
; cpu:the_cpu|M_iw[14]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk0_break_hit~0                                                                                                ; 3       ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk1_break_hit~0                                                                                                ; 3       ;
; cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[1]                                                                                                 ; 3       ;
; cpu:the_cpu|F_iw[0]~11                                                                                                                                                                                 ; 3       ;
; cpu:the_cpu|F_iw[3]~9                                                                                                                                                                                  ; 3       ;
; cpu:the_cpu|F_iw[5]~8                                                                                                                                                                                  ; 3       ;
; cpu:the_cpu|D_pc[23]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_iw[10]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_ctrl_ignore_dst                                                                                                                                                                          ; 3       ;
; cpu:the_cpu|D_wr_dst_reg~0                                                                                                                                                                             ; 3       ;
; cpu:the_cpu|D_iw[22]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_iw[24]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_iw[25]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_iw[26]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|D_iw[23]                                                                                                                                                                                   ; 3       ;
; cpu:the_cpu|F_iw[2]~7                                                                                                                                                                                  ; 3       ;
; cpu:the_cpu|F_iw[1]~6                                                                                                                                                                                  ; 3       ;
; cpu:the_cpu|F_ctrl_implicit_dst_retaddr~8                                                                                                                                                              ; 3       ;
; cpu:the_cpu|E_dst_regnum[4]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|E_dst_regnum[2]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|E_dst_regnum[3]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|E_dst_regnum[0]                                                                                                                                                                            ; 3       ;
; cpu:the_cpu|E_dst_regnum[1]                                                                                                                                                                            ; 3       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------------+----------------------------------------------------------------+
; Name                                                                                                                                                                                                                             ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF                                        ; Location                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------------+----------------------------------------------------------------+
; cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_2of1:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; Simple Dual Port ; Single Clock ; 256          ; 2            ; 256          ; 2            ; yes                    ; no                      ; yes                    ; yes                     ; 512   ; 256                         ; 2                           ; 256                         ; 2                           ; 512                 ; 1    ; cpu_bht_ram.mif                            ; M9K_X13_Y9_N0                                                  ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; Dual Clocks  ; 1024         ; 32           ; 1024         ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 32768 ; 1024                        ; 32                          ; 1024                        ; 32                          ; 32768               ; 4    ; None                                       ; M9K_X13_Y11_N0, M9K_X13_Y13_N0, M9K_X13_Y12_N0, M9K_X13_Y14_N0 ;
; cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_c4g1:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; Simple Dual Port ; Single Clock ; 128          ; 23           ; 128          ; 23           ; yes                    ; no                      ; yes                    ; no                      ; 2944  ; 128                         ; 23                          ; 128                         ; 23                          ; 2944                ; 1    ; cpu_ic_tag_ram.mif                         ; M9K_X25_Y12_N0                                                 ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_6472:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; Single Clock ; 256          ; 32           ; 256          ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 8192  ; 256                         ; 32                          ; 256                         ; 32                          ; 8192                ; 2    ; cpu_ociram_default_contents.mif            ; M9K_X25_Y17_N0, M9K_X25_Y18_N0                                 ;
; cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_26f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; Single Clock ; 32           ; 32           ; 32           ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 1024  ; 32                          ; 32                          ; 32                          ; 32                          ; 1024                ; 1    ; cpu_rf_ram_a.mif                           ; M9K_X25_Y11_N0                                                 ;
; cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_36f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; Single Clock ; 32           ; 32           ; 32           ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 1024  ; 32                          ; 32                          ; 32                          ; 32                          ; 1024                ; 1    ; cpu_rf_ram_b.mif                           ; M9K_X25_Y10_N0                                                 ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_i851:auto_generated|ALTSYNCRAM                                                                                                     ; AUTO ; ROM              ; Single Clock ; 256          ; 32           ; --           ; --           ; yes                    ; no                      ; --                     ; --                      ; 8192  ; 256                         ; 32                          ; --                          ; --                          ; 8192                ; 1    ; epcs_flash_controller_0_boot_rom_synth.hex ; M9K_X13_Y17_N0                                                 ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                 ; AUTO ; Simple Dual Port ; Dual Clocks  ; 64           ; 8            ; 64           ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 512   ; 64                          ; 8                           ; 64                          ; 8                           ; 512                 ; 1    ; None                                       ; M9K_X25_Y20_N0                                                 ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                 ; AUTO ; Simple Dual Port ; Dual Clocks  ; 64           ; 8            ; 64           ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 512   ; 64                          ; 8                           ; 64                          ; 8                           ; 512                 ; 1    ; None                                       ; M9K_X25_Y19_N0                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------------+----------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |nios|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_i851:auto_generated|ALTSYNCRAM                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
;0;(00000000000000010111000000111010) (270072) (94266) (1703A)    ;(00000100110000000000000001110100) (460000164) (79691892) (4C00074)   ;(10011000000000010100100000111010) (1664917238) (-1744746438) (-6-7-15-14-11-7-12-6)   ;(10011100111111111111100000000100) (2142447170) (-1660946428) (-6-3000-7-15-12)   ;(10011000001111111111110100011110) (1682449602) (-1740636898) (-6-7-1200-2-14-2)   ;(00000000000000000010000000111010) (20072) (8250) (203A)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000100101000000110) (45006) (18950) (4A06)   ;
;8;(00000001011111111111111111000100) (137777704) (25165764) (17FFFC4)    ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000001101100000110) (15406) (6918) (1B06)   ;(00110000000001111000100000111010) (1706736776) (805799994) (3007883A)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000001100000000110) (14006) (6150) (1806)   ;(00110000000010011000100000111010) (1707336776) (805931066) (3009883A)   ;(00011000000000000000010000100110) (-1294965250) (402654246) (18000426)   ;
;16;(00011001011111111111111100100110) (-1157189850) (427818790) (197FFF26)    ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000010101000000110) (25006) (10758) (2A06)   ;(00000000001111111111010100000110) (17772406) (4191494) (3FF506)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000000101000000110) (5006) (2566) (A06)   ;(00100000001111101110100000111010) (-277403224) (540993594) (203EE83A)   ;(00000000001111111111111100000110) (17777406) (4194054) (3FFF06)   ;
;24;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)    ;(00000000000000000000011000000110) (3006) (1542) (606)   ;(00000000001111111111111100000110) (17777406) (4194054) (3FFF06)   ;(00000011000000010000000000000100) (300200004) (50397188) (3010004)   ;(10010011000000000000001100110101) (964674631) (-1828715723) (-6-12-15-15-15-12-12-11)   ;(00000010110000001100000000110100) (260140064) (46186548) (2C0C034)   ;(01011000100101101011000000111010) (898046424) (1486270522) (5896B03A)   ;(00000000000000000000011100000110) (3406) (1798) (706)   ;
;32;(10111101110000000000000100000100) (1929706274) (-1111490300) (-4-2-3-15-15-14-15-12)    ;(10010011000000000000001000110111) (964674233) (-1828715977) (-6-12-15-15-15-13-12-9)   ;(01100011000000000000100000001100) (-2142446930) (1660946444) (6300080C)   ;(01100000001111111111110100100110) (1870292798) (1614806310) (603FFD26)   ;(10010000000000000000001100110101) (664674631) (-1879047371) (-6-15-15-15-15-12-12-11)   ;(10111000000000000110100000111010) (1369769942) (-1207932870) (-4-7-15-15-9-7-12-6)   ;(00000000000101111000100000111010) (5704072) (1542202) (17883A)   ;(10111010000000000000000100000100) (1569706274) (-1174404860) (-4-5-15-15-15-14-15-12)   ;
;40;(00000000000011011000100000111010) (3304072) (886842) (D883A)    ;(00000101000000000000000100000100) (500000404) (83886340) (5000104)   ;(01011000000101100001001000111010) (857927424) (1477841466) (5816123A)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000000000000000011000000110) (3006) (1542) (606)   ;(00110010100011001011000000111010) (1948162776) (848080954) (328CB03A)   ;(00110000000011000001011000111010) (1708045776) (806098490) (300C163A)   ;(10100101001111111111111111000100) (-1112516426) (-1522532412) (-5-10-12000-3-12)   ;
;48;(10100000001111111111100100011110) (-1612519694) (-1606420194) (-5-15-1200-6-14-2)    ;(01000000000000000110100000111010) (-2147419576) (1073768506) (4000683A)   ;(00000000000101111000100000111010) (5704072) (1542202) (17883A)   ;(10111101110000000000000100000100) (1929706274) (-1111490300) (-4-2-3-15-15-14-15-12)   ;(10010010010000000000001000110111) (884674233) (-1841298889) (-6-13-11-15-15-13-12-9)   ;(01001010010000000001000000001100) (-927473634) (1245712396) (4A40100C)   ;(01001000001111111111110100100110) (-1129707202) (1212153126) (483FFD26)   ;(10010010110000000000000100110101) (924673631) (-1832910539) (-6-13-3-15-15-14-12-11)   ;
;56;(10010010010000000000001000110111) (884674233) (-1841298889) (-6-13-11-15-15-13-12-9)    ;(01001010010000000010000000001100) (-927463634) (1245716492) (4A40200C)   ;(01001000001111111111110100100110) (-1129707202) (1212153126) (483FFD26)   ;(10010010100000000000000000100011) (904673209) (-1837105117) (-6-13-7-15-15-15-13-13)   ;(10111000000000000110100000111010) (1369769942) (-1207932870) (-4-7-15-15-9-7-12-6)   ;(10111101110000000000000100000100) (1929706274) (-1111490300) (-4-2-3-15-15-14-15-12)   ;(00011001000001111000100000111010) (-1193263224) (419924026) (1907883A)   ;(00011000111111111111111111000100) (-1217189592) (419430340) (18FFFFC4)   ;
;64;(10010010010000000000001000110111) (884674233) (-1841298889) (-6-13-11-15-15-13-12-9)    ;(01001010010000000001000000001100) (-927473634) (1245712396) (4A40100C)   ;(01001000001111111111110100100110) (-1129707202) (1212153126) (483FFD26)   ;(10010000000000000000000100110101) (664673631) (-1879047883) (-6-15-15-15-15-14-12-11)   ;(10010010010000000000001000110111) (884674233) (-1841298889) (-6-13-11-15-15-13-12-9)   ;(01001010010000000010000000001100) (-927463634) (1245716492) (4A40200C)   ;(01001000001111111111110100100110) (-1129707202) (1212153126) (483FFD26)   ;(10010010010000000000000000110111) (884673233) (-1841299401) (-6-13-11-15-15-15-12-9)   ;
;72;(10010000000000000000000100110101) (664673631) (-1879047883) (-6-15-15-15-15-14-12-11)    ;(00100010010000000000000000100101) (-74967251) (574619685) (22400025)   ;(00100001000000000000000001000100) (-194967192) (553648196) (21000044)   ;(00100000111111111111100000011110) (-217193260) (553646110) (20FFF81E)   ;(10010010010000000000001000110111) (884674233) (-1841298889) (-6-13-11-15-15-13-12-9)   ;(01001010010000000010000000001100) (-927463634) (1245716492) (4A40200C)   ;(01001000001111111111110100100110) (-1129707202) (1212153126) (483FFD26)   ;(10010010010000000000000000110111) (884673233) (-1841299401) (-6-13-11-15-15-15-12-9)   ;
;80;(00100010010000000000000000100101) (-74967251) (574619685) (22400025)    ;(10111000000000000110100000111010) (1369769942) (-1207932870) (-4-7-15-15-9-7-12-6)   ;(10111011010000000000000100000100) (1689706274) (-1153433340) (-4-4-11-15-15-14-15-12)   ;(00000000000111001110000000111010) (7160072) (1892410) (1CE03A)   ;(01110100100000001111111111010100) (-2273220) (1954611156) (7480FFD4)   ;(10010100100000000000000001000100) (1104673270) (-1803550652) (-6-11-7-15-15-15-11-12)   ;(00000000100000000000000000000100) (40000004) (8388612) (800004)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;
;88;(00000000001111111100001000000110) (17741006) (4178438) (3FC206)    ;(00000100000000000000100000000100) (400004004) (67110916) (4000804)   ;(00000011100000000011111111000100) (340037704) (58736580) (3803FC4)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111101010100000110) (17752406) (4183302) (3FD506)   ;(01010011100000000010010000011110) (192538388) (1400906782) (5380241E)   ;(10000100001111111111111111000100) (-917549130) (-2076180540) (-7-11-12000-3-12)   ;(10000000001111111111101100011110) (-1317551398) (-2143290594) (-7-15-1200-4-14-2)   ;
;96;(00000100000000000000011001000100) (400003104) (67110468) (4000644)    ;(00000011100000000000000000000100) (340000004) (58720260) (3800004)   ;(00000000100000000000110000000100) (40006004) (8391684) (800C04)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111011101100000110) (17735406) (4176646) (3FBB06)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111011010000000110) (17732006) (4174854) (3FB406)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;
;104;(00000000001111111100100100000110) (17744406) (4180230) (3FC906)    ;(01010010100000000000100000001100) (92520366) (1384122380) (5280080C)   ;(01010000000101001001011010111010) (-142370376) (1343526586) (501496BA)   ;(01110000000111001101000001111010) (-435300772) (1880936570) (701CD07A)   ;(01110010100111001011000000111010) (-195320872) (1922871354) (729CB03A)   ;(10000100001111111111111111000100) (-917549130) (-2076180540) (-7-11-12000-3-12)   ;(10000000001111111111100000011110) (-1317552798) (-2143291362) (-7-15-1200-7-14-2)   ;(00000100000000000000000111000100) (400000704) (67109316) (40001C4)   ;
;112;(00000000100000000000100001000100) (40004104) (8390724) (800844)    ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111010110100000110) (17726406) (4173062) (3FAD06)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111010011000000110) (17723006) (4171270) (3FA606)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111011101100000110) (17735406) (4176646) (3FBB06)   ;(01010010100000000000010000001100) (92518366) (1384121356) (5280040C)   ;
;120;(01010000000101001001011011111010) (-142370276) (1343526650) (501496FA)    ;(01110000000111001101000001111010) (-435300772) (1880936570) (701CD07A)   ;(01110010100111001011000000111010) (-195320872) (1922871354) (729CB03A)   ;(10000100001111111111111111000100) (-917549130) (-2076180540) (-7-11-12000-3-12)   ;(10000000001111111111100000011110) (-1317552798) (-2143291362) (-7-15-1200-7-14-2)   ;(01110000000001011000100000111010) (-441146872) (1879410746) (7005883A)   ;(00000011101111111111111111000100) (357777704) (62914500) (3BFFFC4)   ;(00010011101111111001100000100110) (-1937253250) (331323430) (13BF9826)   ;
;128;(00010000100000000000000111000100) (2040000704) (276824516) (108001C4)    ;(00010000000001001101000011111010) (2001150372) (268751098) (1004D0FA)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111001110000000110) (17716006) (4168710) (3F9C06)   ;(00000000001011101110000000111010) (13560072) (3072058) (2EE03A)   ;(00000000001111111001010100000110) (17712406) (4166918) (3F9506)   ;(01101000000000000110100000111010) (-1442386872) (1744857146) (6800683A)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;136;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;144;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;152;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;160;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;168;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;176;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;184;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;192;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;200;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;208;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;216;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;224;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;232;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;240;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;
;248;(00000000000000000000000000000000) (0) (0) (00)    ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;(00000000000000000000000000000000) (0) (0) (00)   ;




+-----------------------------------------------------------------------------------------------+
; Fitter DSP Block Usage Summary                                                                ;
+---------------------------------------+-------------+---------------------+-------------------+
; Statistic                             ; Number Used ; Available per Block ; Maximum Available ;
+---------------------------------------+-------------+---------------------+-------------------+
; Simple Multipliers (9-bit)            ; 0           ; 2                   ; 112               ;
; Simple Multipliers (18-bit)           ; 2           ; 1                   ; 56                ;
; Embedded Multiplier Blocks            ; 2           ; --                  ; 56                ;
; Embedded Multiplier 9-bit elements    ; 4           ; 2                   ; 112               ;
; Signed Embedded Multipliers           ; 0           ; --                  ; --                ;
; Unsigned Embedded Multipliers         ; 2           ; --                  ; --                ;
; Mixed Sign Embedded Multipliers       ; 0           ; --                  ; --                ;
; Variable Sign Embedded Multipliers    ; 0           ; --                  ; --                ;
; Dedicated Input Shift Register Chains ; 0           ; --                  ; --                ;
+---------------------------------------+-------------+---------------------+-------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DSP Block Details                                                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
; Name                                                                                                                                             ; Mode                       ; Location          ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_out3     ; Simple Multiplier (18-bit) ; DSPOUT_X18_Y6_N2  ;                     ; No                             ;                       ;                       ;                   ; yes             ;
;    cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2 ;                            ; DSPMULT_X18_Y6_N0 ; Unsigned            ;                                ; yes                   ; yes                   ; no                ;                 ;
; cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_out3     ; Simple Multiplier (18-bit) ; DSPOUT_X18_Y5_N2  ;                     ; No                             ;                       ;                       ;                   ; yes             ;
;    cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|mac_mult2 ;                            ; DSPMULT_X18_Y5_N0 ; Unsigned            ;                                ; yes                   ; yes                   ; no                ;                 ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+-------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+


+------------------------------------------------------+
; Interconnect Usage Summary                           ;
+----------------------------+-------------------------+
; Interconnect Resource Type ; Usage                   ;
+----------------------------+-------------------------+
; Block interconnects        ; 7,754 / 47,787 ( 16 % ) ;
; C16 interconnects          ; 141 / 1,804 ( 8 % )     ;
; C4 interconnects           ; 4,862 / 31,272 ( 16 % ) ;
; Direct links               ; 842 / 47,787 ( 2 % )    ;
; Global clocks              ; 8 / 20 ( 40 % )         ;
; Local interconnects        ; 2,171 / 15,408 ( 14 % ) ;
; R24 interconnects          ; 188 / 1,775 ( 11 % )    ;
; R4 interconnects           ; 6,140 / 41,310 ( 15 % ) ;
+----------------------------+-------------------------+


+-----------------------------------------------------------------------------+
; LAB Logic Elements                                                          ;
+---------------------------------------------+-------------------------------+
; Number of Logic Elements  (Average = 12.84) ; Number of LABs  (Total = 339) ;
+---------------------------------------------+-------------------------------+
; 1                                           ; 27                            ;
; 2                                           ; 9                             ;
; 3                                           ; 8                             ;
; 4                                           ; 9                             ;
; 5                                           ; 2                             ;
; 6                                           ; 0                             ;
; 7                                           ; 5                             ;
; 8                                           ; 7                             ;
; 9                                           ; 5                             ;
; 10                                          ; 8                             ;
; 11                                          ; 7                             ;
; 12                                          ; 9                             ;
; 13                                          ; 7                             ;
; 14                                          ; 9                             ;
; 15                                          ; 11                            ;
; 16                                          ; 216                           ;
+---------------------------------------------+-------------------------------+


+--------------------------------------------------------------------+
; LAB-wide Signals                                                   ;
+------------------------------------+-------------------------------+
; LAB-wide Signals  (Average = 2.68) ; Number of LABs  (Total = 339) ;
+------------------------------------+-------------------------------+
; 1 Async. clear                     ; 271                           ;
; 1 Clock                            ; 310                           ;
; 1 Clock enable                     ; 170                           ;
; 1 Sync. clear                      ; 10                            ;
; 1 Sync. load                       ; 55                            ;
; 2 Async. clears                    ; 6                             ;
; 2 Clock enables                    ; 73                            ;
; 2 Clocks                           ; 12                            ;
+------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Signals Sourced                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Signals Sourced  (Average = 20.34) ; Number of LABs  (Total = 339) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 0                             ;
; 1                                            ; 11                            ;
; 2                                            ; 16                            ;
; 3                                            ; 1                             ;
; 4                                            ; 10                            ;
; 5                                            ; 2                             ;
; 6                                            ; 7                             ;
; 7                                            ; 4                             ;
; 8                                            ; 3                             ;
; 9                                            ; 0                             ;
; 10                                           ; 2                             ;
; 11                                           ; 3                             ;
; 12                                           ; 1                             ;
; 13                                           ; 5                             ;
; 14                                           ; 7                             ;
; 15                                           ; 9                             ;
; 16                                           ; 4                             ;
; 17                                           ; 4                             ;
; 18                                           ; 6                             ;
; 19                                           ; 11                            ;
; 20                                           ; 17                            ;
; 21                                           ; 13                            ;
; 22                                           ; 22                            ;
; 23                                           ; 29                            ;
; 24                                           ; 26                            ;
; 25                                           ; 23                            ;
; 26                                           ; 24                            ;
; 27                                           ; 17                            ;
; 28                                           ; 17                            ;
; 29                                           ; 16                            ;
; 30                                           ; 8                             ;
; 31                                           ; 5                             ;
; 32                                           ; 16                            ;
+----------------------------------------------+-------------------------------+


+----------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                          ;
+--------------------------------------------------+-------------------------------+
; Number of Signals Sourced Out  (Average = 10.04) ; Number of LABs  (Total = 339) ;
+--------------------------------------------------+-------------------------------+
; 0                                                ; 0                             ;
; 1                                                ; 30                            ;
; 2                                                ; 10                            ;
; 3                                                ; 8                             ;
; 4                                                ; 12                            ;
; 5                                                ; 8                             ;
; 6                                                ; 11                            ;
; 7                                                ; 24                            ;
; 8                                                ; 31                            ;
; 9                                                ; 21                            ;
; 10                                               ; 21                            ;
; 11                                               ; 23                            ;
; 12                                               ; 27                            ;
; 13                                               ; 26                            ;
; 14                                               ; 20                            ;
; 15                                               ; 16                            ;
; 16                                               ; 18                            ;
; 17                                               ; 13                            ;
; 18                                               ; 8                             ;
; 19                                               ; 2                             ;
; 20                                               ; 4                             ;
; 21                                               ; 0                             ;
; 22                                               ; 0                             ;
; 23                                               ; 0                             ;
; 24                                               ; 3                             ;
; 25                                               ; 1                             ;
; 26                                               ; 1                             ;
; 27                                               ; 0                             ;
; 28                                               ; 0                             ;
; 29                                               ; 0                             ;
; 30                                               ; 0                             ;
; 31                                               ; 0                             ;
; 32                                               ; 1                             ;
+--------------------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Distinct Inputs                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Distinct Inputs  (Average = 20.76) ; Number of LABs  (Total = 339) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 0                             ;
; 1                                            ; 1                             ;
; 2                                            ; 5                             ;
; 3                                            ; 7                             ;
; 4                                            ; 14                            ;
; 5                                            ; 9                             ;
; 6                                            ; 7                             ;
; 7                                            ; 7                             ;
; 8                                            ; 3                             ;
; 9                                            ; 3                             ;
; 10                                           ; 8                             ;
; 11                                           ; 12                            ;
; 12                                           ; 6                             ;
; 13                                           ; 5                             ;
; 14                                           ; 7                             ;
; 15                                           ; 5                             ;
; 16                                           ; 8                             ;
; 17                                           ; 4                             ;
; 18                                           ; 17                            ;
; 19                                           ; 9                             ;
; 20                                           ; 16                            ;
; 21                                           ; 13                            ;
; 22                                           ; 14                            ;
; 23                                           ; 10                            ;
; 24                                           ; 9                             ;
; 25                                           ; 5                             ;
; 26                                           ; 7                             ;
; 27                                           ; 10                            ;
; 28                                           ; 11                            ;
; 29                                           ; 6                             ;
; 30                                           ; 14                            ;
; 31                                           ; 26                            ;
; 32                                           ; 26                            ;
; 33                                           ; 18                            ;
; 34                                           ; 15                            ;
+----------------------------------------------+-------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 12    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 18    ;
+----------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                 ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------------+------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                           ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------------+------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                    ; I/O  ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.               ; I/O  ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                   ; I/O  ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                ; I/O  ;                   ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                     ; I/O  ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.       ; I/O  ;                   ;
; Pass         ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                ; I/O  ;                   ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                     ; I/O  ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Pass         ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.       ; I/O  ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                      ; I/O  ;                   ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                     ; I/O  ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found. ; I/O  ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry assignments found.       ; I/O  ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                       ; I/O  ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                       ; I/O  ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                       ; I/O  ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                ; I/O  ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.       ; I/O  ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.               ; I/O  ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------------+------+-------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules                             ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+---------------------------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass                            ; 53           ; 37           ; 53           ; 0            ; 0            ; 106       ; 53           ; 0            ; 106       ; 106       ; 0            ; 0            ; 0            ; 31           ; 56           ; 0            ; 0            ; 56           ; 31           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 106       ; 0            ; 0            ;
; Total Unchecked                       ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable                    ; 53           ; 69           ; 53           ; 106          ; 106          ; 0         ; 53           ; 106          ; 0         ; 0         ; 106          ; 106          ; 106          ; 75           ; 50           ; 106          ; 106          ; 50           ; 75           ; 106          ; 106          ; 106          ; 106          ; 106          ; 106          ; 106          ; 106          ; 0         ; 106          ; 106          ;
; Total Fail                            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; altpll_0_c0_out                       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altpll_0_c1_out                       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; locked_from_the_altpll_0              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; phasedone_from_the_altpll_0           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; dclk_from_the_epcs_flash_controller_0 ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; sce_from_the_epcs_flash_controller_0  ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; sdo_from_the_epcs_flash_controller_0  ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_lcd_cs              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_lcd_rs              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_lcd_wr              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_reset               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_sd_cs               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[0]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[1]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[2]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[3]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[4]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[5]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[6]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[7]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[8]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[9]           ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[10]          ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[11]          ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_addr_from_the_sdram_0[12]          ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_ba_from_the_sdram_0[0]             ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_ba_from_the_sdram_0[1]             ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_cas_n_from_the_sdram_0             ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_cke_from_the_sdram_0               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_cs_n_from_the_sdram_0              ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dqm_from_the_sdram_0[0]            ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dqm_from_the_sdram_0[1]            ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_ras_n_from_the_sdram_0             ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_we_n_from_the_sdram_0              ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MOSI_from_the_spi_lcd22               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SCLK_from_the_spi_lcd22               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SS_n_from_the_spi_lcd22               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MOSI_from_the_spi_sdcard              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SCLK_from_the_spi_sdcard              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SS_n_from_the_spi_sdcard              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MOSI_from_the_spi_touch               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SCLK_from_the_spi_touch               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SS_n_from_the_spi_touch               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; out_port_from_the_touch_cs            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; txd_from_the_uart_9600                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_DS18B20    ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[0]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[1]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[2]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[3]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[4]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[5]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[6]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pa[7]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[0]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[1]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[2]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[3]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[4]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[5]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[6]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pb[7]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[0]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[1]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[2]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[3]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[4]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[5]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[6]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pc[7]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[0]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[1]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[2]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[3]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[4]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[5]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[6]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; bidir_port_to_and_from_the_pd[7]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[0]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[1]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[2]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[3]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[4]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[5]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[6]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[7]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[8]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[9]      ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[10]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[11]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[12]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[13]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[14]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; zs_dq_to_and_from_the_sdram_0[15]     ; Pass         ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; clk_ex                                ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; reset_n                               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; in_port_to_the_touch_irq              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MISO_to_the_spi_lcd22                 ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MISO_to_the_spi_touch                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; MISO_to_the_spi_sdcard                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; data0_to_the_epcs_flash_controller_0  ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; rxd_to_the_uart_9600                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tms                   ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tck                   ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdi                   ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdo                   ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+---------------------------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+------------------------------------------------------------------+---------------------+
; Option                                                           ; Setting             ;
+------------------------------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                 ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                 ;
; Enable device-wide output enable (DEV_OE)                        ; Off                 ;
; Enable INIT_DONE output                                          ; Off                 ;
; Configuration scheme                                             ; Active Serial       ;
; Error detection CRC                                              ; Off                 ;
; Enable open drain on CRC_ERROR pin                               ; Off                 ;
; Enable input tri-state on active configuration pins in user mode ; Off                 ;
; Configuration Voltage Level                                      ; Auto                ;
; Force Configuration Voltage Level                                ; Off                 ;
; nCEO                                                             ; Unreserved          ;
; Data[0]                                                          ; Unreserved          ;
; Data[1]/ASDO                                                     ; Unreserved          ;
; Data[7..2]                                                       ; Compiler configured ;
; FLASH_nCE/nCSO                                                   ; Unreserved          ;
; Other Active Parallel pins                                       ; Unreserved          ;
; DCLK                                                             ; Unreserved          ;
; Base pin-out file on sameframe device                            ; Off                 ;
+------------------------------------------------------------------+---------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Fri May 04 13:04:55 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off nios -c nios
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EP3C16Q240C8 for design "nios"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Implemented PLL "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|pll7" as Cyclone III PLL type
    Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0] port
    Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -100 degrees (-5556 ps) for altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[1] port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP3C25Q240C8 is compatible
    Info: Device EP3C40Q240C8 is compatible
Info: DATA[0] dual-purpose pin not reserved
Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning: No exact pin location assignment(s) for 49 pins of 102 total pins
    Info: Pin altpll_0_c0_out not assigned to an exact location on the device
    Info: Pin locked_from_the_altpll_0 not assigned to an exact location on the device
    Info: Pin phasedone_from_the_altpll_0 not assigned to an exact location on the device
    Info: Pin out_port_from_the_lcd_wr not assigned to an exact location on the device
    Info: Pin out_port_from_the_sd_cs not assigned to an exact location on the device
    Info: Pin SS_n_from_the_spi_lcd22 not assigned to an exact location on the device
    Info: Pin MOSI_from_the_spi_sdcard not assigned to an exact location on the device
    Info: Pin SCLK_from_the_spi_sdcard not assigned to an exact location on the device
    Info: Pin SS_n_from_the_spi_sdcard not assigned to an exact location on the device
    Info: Pin MOSI_from_the_spi_touch not assigned to an exact location on the device
    Info: Pin SCLK_from_the_spi_touch not assigned to an exact location on the device
    Info: Pin SS_n_from_the_spi_touch not assigned to an exact location on the device
    Info: Pin txd_from_the_uart_9600 not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_DS18B20 not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[0] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[1] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[2] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[3] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[4] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[5] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[6] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pa[7] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[0] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[1] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[2] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[3] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[4] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[5] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[6] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pb[7] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[0] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[1] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[2] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[3] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[4] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[5] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[6] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pc[7] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[0] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[1] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[2] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[3] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[4] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[5] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[6] not assigned to an exact location on the device
    Info: Pin bidir_port_to_and_from_the_pd[7] not assigned to an exact location on the device
    Info: Pin MISO_to_the_spi_touch not assigned to an exact location on the device
    Info: Pin MISO_to_the_spi_sdcard not assigned to an exact location on the device
    Info: Pin rxd_to_the_uart_9600 not assigned to an exact location on the device
Info: Timing-driven compilation is using the TimeQuest Timing Analyzer
Info: Evaluating HDL-embedded SDC commands
    Info: Entity alt_jtag_atlantic
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] 
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}] 
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
    Info: Entity altera_std_synchronizer
        Info: set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info: Entity sld_hub
        Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
        Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Info: Reading SDC File: 'cpu.sdc'
Info: Reading SDC File: 'c:/altera/11.0/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc'
Warning: Node: clk_ex was determined to be a clock but was found without an associated clock assignment.
Warning: PLL cross checking found inconsistent PLL clock settings:
    Warning: Node: the_altpll_0|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
    Warning: Node: the_altpll_0|sd1|pll7|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
    Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)
Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info: Found 1 clocks
    Info:   Period   Clock Name
    Info: ======== ============
    Info:  100.000 altera_reserved_tck
Info: Automatically promoted node altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0] (placed in counter C0 of PLL_1)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[1] (placed in counter C1 of PLL_1)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info: Automatically promoted node clk_ex~input (placed in PIN 31 (CLK0, DIFFCLK_0p))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node nios_reset_altpll_0_c0_out_domain_synch_module:nios_reset_altpll_0_c0_out_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sdram_0:the_sdram_0|active_rnw~1
        Info: Destination node sdram_0:the_sdram_0|active_cs_n~0
        Info: Destination node cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break~1
        Info: Destination node sdram_0:the_sdram_0|i_refs[0]
        Info: Destination node sdram_0:the_sdram_0|i_refs[2]
        Info: Destination node sdram_0:the_sdram_0|i_refs[1]
        Info: Destination node cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~0
Info: Automatically promoted node nios_reset_clk_ex_domain_synch_module:nios_reset_clk_ex_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node reset_n_sources~0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node altpll_0:the_altpll_0|prev_reset 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node altpll_0:the_altpll_0|readdata[0]~1
Info: Starting register packing
Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning: Ignoring some wildcard destinations of fast I/O register assignments
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[8]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_cmd[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_cmd[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_cmd[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[10]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[11]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[12]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[13]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[14]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[15]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[4]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[5]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[6]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[7]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Register=ON" to "m_data[9]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
    Info: Wildcard assignment "Fast Output Enable Register=ON" to "oe" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info: Finished register packing
    Extra Info: Packed 10 registers into blocks of type EC
    Extra Info: Packed 64 registers into blocks of type Embedded multiplier block
    Extra Info: Packed 16 registers into blocks of type I/O Input Buffer
    Extra Info: Packed 53 registers into blocks of type I/O Output Buffer
    Extra Info: Created 66 register duplicates
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 49 (unused VREF, 3.3V VCCIO, 3 input, 13 output, 33 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  5 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  2 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  22 pins available
        Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used --  8 pins available
        Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  9 pins available
        Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  22 pins available
        Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available
Warning: PLL "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|pll7" output port clk[0] feeds output pin "altpll_0_c0_out~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: PLL "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|pll7" output port clk[1] feeds output pin "altpll_0_c1_out~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Info: Fitter preparation operations ending: elapsed time is 00:00:09
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Fitter routing operations beginning
Info: Router estimated average interconnect usage is 13% of the available device resources
    Info: Router estimated peak interconnect usage is 49% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning: Following 1 pins must use external clamping diodes.
    Info: Pin data0_to_the_epcs_flash_controller_0 uses I/O standard 3.3-V LVTTL at 24
Warning: 56 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info: Pin bidir_port_to_and_from_the_DS18B20 uses I/O standard 3.3-V LVTTL at 148
    Info: Pin bidir_port_to_and_from_the_pa[0] uses I/O standard 3.3-V LVTTL at 187
    Info: Pin bidir_port_to_and_from_the_pa[1] uses I/O standard 3.3-V LVTTL at 147
    Info: Pin bidir_port_to_and_from_the_pa[2] uses I/O standard 3.3-V LVTTL at 186
    Info: Pin bidir_port_to_and_from_the_pa[3] uses I/O standard 3.3-V LVTTL at 168
    Info: Pin bidir_port_to_and_from_the_pa[4] uses I/O standard 3.3-V LVTTL at 101
    Info: Pin bidir_port_to_and_from_the_pa[5] uses I/O standard 3.3-V LVTTL at 188
    Info: Pin bidir_port_to_and_from_the_pa[6] uses I/O standard 3.3-V LVTTL at 85
    Info: Pin bidir_port_to_and_from_the_pa[7] uses I/O standard 3.3-V LVTTL at 106
    Info: Pin bidir_port_to_and_from_the_pb[0] uses I/O standard 3.3-V LVTTL at 198
    Info: Pin bidir_port_to_and_from_the_pb[1] uses I/O standard 3.3-V LVTTL at 98
    Info: Pin bidir_port_to_and_from_the_pb[2] uses I/O standard 3.3-V LVTTL at 195
    Info: Pin bidir_port_to_and_from_the_pb[3] uses I/O standard 3.3-V LVTTL at 200
    Info: Pin bidir_port_to_and_from_the_pb[4] uses I/O standard 3.3-V LVTTL at 197
    Info: Pin bidir_port_to_and_from_the_pb[5] uses I/O standard 3.3-V LVTTL at 173
    Info: Pin bidir_port_to_and_from_the_pb[6] uses I/O standard 3.3-V LVTTL at 199
    Info: Pin bidir_port_to_and_from_the_pb[7] uses I/O standard 3.3-V LVTTL at 201
    Info: Pin bidir_port_to_and_from_the_pc[0] uses I/O standard 3.3-V LVTTL at 82
    Info: Pin bidir_port_to_and_from_the_pc[1] uses I/O standard 3.3-V LVTTL at 87
    Info: Pin bidir_port_to_and_from_the_pc[2] uses I/O standard 3.3-V LVTTL at 76
    Info: Pin bidir_port_to_and_from_the_pc[3] uses I/O standard 3.3-V LVTTL at 222
    Info: Pin bidir_port_to_and_from_the_pc[4] uses I/O standard 3.3-V LVTTL at 218
    Info: Pin bidir_port_to_and_from_the_pc[5] uses I/O standard 3.3-V LVTTL at 84
    Info: Pin bidir_port_to_and_from_the_pc[6] uses I/O standard 3.3-V LVTTL at 80
    Info: Pin bidir_port_to_and_from_the_pc[7] uses I/O standard 3.3-V LVTTL at 214
    Info: Pin bidir_port_to_and_from_the_pd[0] uses I/O standard 3.3-V LVTTL at 95
    Info: Pin bidir_port_to_and_from_the_pd[1] uses I/O standard 3.3-V LVTTL at 86
    Info: Pin bidir_port_to_and_from_the_pd[2] uses I/O standard 3.3-V LVTTL at 219
    Info: Pin bidir_port_to_and_from_the_pd[3] uses I/O standard 3.3-V LVTTL at 217
    Info: Pin bidir_port_to_and_from_the_pd[4] uses I/O standard 3.3-V LVTTL at 216
    Info: Pin bidir_port_to_and_from_the_pd[5] uses I/O standard 3.3-V LVTTL at 167
    Info: Pin bidir_port_to_and_from_the_pd[6] uses I/O standard 3.3-V LVTTL at 221
    Info: Pin bidir_port_to_and_from_the_pd[7] uses I/O standard 3.3-V LVTTL at 207
    Info: Pin zs_dq_to_and_from_the_sdram_0[0] uses I/O standard 3.3-V LVTTL at 13
    Info: Pin zs_dq_to_and_from_the_sdram_0[1] uses I/O standard 3.3-V LVTTL at 9
    Info: Pin zs_dq_to_and_from_the_sdram_0[2] uses I/O standard 3.3-V LVTTL at 18
    Info: Pin zs_dq_to_and_from_the_sdram_0[3] uses I/O standard 3.3-V LVTTL at 21
    Info: Pin zs_dq_to_and_from_the_sdram_0[4] uses I/O standard 3.3-V LVTTL at 22
    Info: Pin zs_dq_to_and_from_the_sdram_0[5] uses I/O standard 3.3-V LVTTL at 37
    Info: Pin zs_dq_to_and_from_the_sdram_0[6] uses I/O standard 3.3-V LVTTL at 38
    Info: Pin zs_dq_to_and_from_the_sdram_0[7] uses I/O standard 3.3-V LVTTL at 39
    Info: Pin zs_dq_to_and_from_the_sdram_0[8] uses I/O standard 3.3-V LVTTL at 159
    Info: Pin zs_dq_to_and_from_the_sdram_0[9] uses I/O standard 3.3-V LVTTL at 160
    Info: Pin zs_dq_to_and_from_the_sdram_0[10] uses I/O standard 3.3-V LVTTL at 161
    Info: Pin zs_dq_to_and_from_the_sdram_0[11] uses I/O standard 3.3-V LVTTL at 162
    Info: Pin zs_dq_to_and_from_the_sdram_0[12] uses I/O standard 3.3-V LVTTL at 164
    Info: Pin zs_dq_to_and_from_the_sdram_0[13] uses I/O standard 3.3-V LVTTL at 166
    Info: Pin zs_dq_to_and_from_the_sdram_0[14] uses I/O standard 3.3-V LVTTL at 169
    Info: Pin zs_dq_to_and_from_the_sdram_0[15] uses I/O standard 3.3-V LVTTL at 171
    Info: Pin clk_ex uses I/O standard 3.3-V LVTTL at 31
    Info: Pin reset_n uses I/O standard 3.3-V LVTTL at 6
    Info: Pin in_port_to_the_touch_irq uses I/O standard 3.3-V LVTTL at 63
    Info: Pin MISO_to_the_spi_lcd22 uses I/O standard 3.3-V LVTTL at 78
    Info: Pin MISO_to_the_spi_touch uses I/O standard 3.3-V LVTTL at 70
    Info: Pin MISO_to_the_spi_sdcard uses I/O standard 3.3-V LVTTL at 224
    Info: Pin rxd_to_the_uart_9600 uses I/O standard 3.3-V LVTTL at 109
Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447.
    Info: Pin data0_to_the_epcs_flash_controller_0 uses I/O standard 3.3-V LVTTL at 24
Info: Generated suppressed messages file E:/Program/EP3C16/nios/LCD22+epcs16+sdram+bigpicture/nios.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 18 warnings
    Info: Peak virtual memory: 422 megabytes
    Info: Processing ended: Fri May 04 13:05:19 2012
    Info: Elapsed time: 00:00:24
    Info: Total CPU time (on all processors): 00:00:26


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/Program/EP3C16/nios/LCD22+epcs16+sdram+bigpicture/nios.fit.smsg.


