| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst1|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst1 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|sopc_reset_clk_0_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_timer |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_timer_s1 |
73 |
1 |
18 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sysid |
3 |
18 |
1 |
18 |
32 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sysid_control_slave |
55 |
1 |
2 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart|the_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart |
38 |
10 |
23 |
10 |
36 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_avalon_jtag_slave |
92 |
1 |
2 |
1 |
78 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_do_spi |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_do_spi_s1 |
24 |
1 |
2 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_di_spi |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_di_spi_s1 |
57 |
1 |
33 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cs_spi |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cs_spi_s1 |
57 |
1 |
33 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper|the_cpu_0_jtag_debug_module_sysclk |
43 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper|the_cpu_0_jtag_debug_module_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper |
123 |
0 |
0 |
0 |
53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component|the_altsyncram|auto_generated |
92 |
0 |
0 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component |
92 |
2 |
0 |
2 |
72 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im |
97 |
36 |
17 |
36 |
48 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_pib |
39 |
20 |
38 |
20 |
19 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|the_cpu_0_oci_test_bench |
36 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc_fifocount |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc_fifowp |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count_tm_count |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo |
151 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dtrace |
104 |
0 |
93 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_itrace |
25 |
17 |
23 |
17 |
87 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dbrk |
89 |
0 |
0 |
0 |
93 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_xbrk |
55 |
5 |
52 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_break |
52 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_avalon_reg |
49 |
0 |
28 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component|the_altsyncram|auto_generated |
90 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component |
90 |
2 |
0 |
2 |
64 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem |
93 |
0 |
6 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_nios2_oci |
160 |
0 |
0 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|cpu_0_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|cpu_0_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|cpu_0_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|cpu_0_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0|the_cpu_0_test_bench |
463 |
3 |
426 |
3 |
34 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0 |
149 |
0 |
29 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_instruction_master |
133 |
0 |
5 |
0 |
52 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_data_master |
280 |
29 |
30 |
29 |
84 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_jtag_debug_module |
114 |
2 |
4 |
2 |
92 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_clk_spi |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_clk_spi_s1 |
57 |
1 |
33 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART|the_RS232_UART_regs |
41 |
9 |
6 |
9 |
40 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART|the_RS232_UART_rx|the_RS232_UART_rx_stimulus_source |
14 |
0 |
13 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART|the_RS232_UART_rx |
16 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART|the_RS232_UART_tx |
24 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RS232_UART_s1 |
74 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_ROM|the_altsyncram|auto_generated |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_ROM |
53 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_ROM_s1 |
113 |
1 |
4 |
1 |
94 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RAM|the_altsyncram|auto_generated|mux2 |
130 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RAM|the_altsyncram|auto_generated|decode3 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RAM|the_altsyncram|auto_generated |
54 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RAM |
56 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_RAM_s1 |
112 |
1 |
4 |
1 |
97 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst |
4 |
1 |
0 |
1 |
4 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |