Altera SOPC Builder Version 10.10 Build 153
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved.


No .sopc_builder configuration file(!)
# 2012.02.04 15:56:17 (*) mk_custom_sdk starting
# 2012.02.04 15:56:17 (*) Reading project E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS.ptf.

# 2012.02.04 15:56:18 (*) Finding all CPUs
# 2012.02.04 15:56:18 (*) Finding all available components
# 2012.02.04 15:56:18 (*) Reading E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/.sopc_builder/install.ptf

# 2012.02.04 15:56:18 (*) Found 63 components

# 2012.02.04 15:56:18 (*) Finding all peripherals

# 2012.02.04 15:56:19 (*) Finding software components

# 2012.02.04 15:56:19 (*) (Legacy SDK Generation Skipped)
# 2012.02.04 15:56:19 (*) (All TCL Script Generation Skipped)
# 2012.02.04 15:56:19 (*) (No Libraries Built)
# 2012.02.04 15:56:19 (*) (Contents Generation Skipped)
# 2012.02.04 15:56:19 (*) mk_custom_sdk finishing

# 2012.02.04 15:56:19 (*) Starting generation for system: NIOS.

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# 2012.02.04 15:56:20 (*) Running Generator Program for cpu_0

# 2012.02.04 15:56:22 (*) Starting Nios II generation
# 2012.02.04 15:56:23 (*)   Checking for plaintext license.
# 2012.02.04 15:56:23 (*)   Plaintext license not found.
# 2012.02.04 15:56:23 (*)   Checking for encrypted license (non-evaluation).
# 2012.02.04 15:56:23 (*)   Encrypted license found.  SOF will not be time-limited.
# 2012.02.04 15:56:23 (*)   Getting CPU configuration settings
# 2012.02.04 15:56:23 (*)   Elaborating CPU configuration settings
# 2012.02.04 15:56:23 (*)   Creating all objects for CPU

# 2012.02.04 15:56:23 (*)     Testbench
# 2012.02.04 15:56:24 (*)     Instruction decoding
# 2012.02.04 15:56:24 (*)       Instruction fields
# 2012.02.04 15:56:24 (*)       Instruction decodes
# 2012.02.04 15:56:26 (*)       Signals for RTL simulation waveforms
# 2012.02.04 15:56:26 (*)       Instruction controls
# 2012.02.04 15:56:26 (*)     Pipeline frontend
# 2012.02.04 15:56:26 (*)     Pipeline backend
# 2012.02.04 15:56:33 (*)   Generating HDL from CPU objects
# 2012.02.04 15:56:38 (*)   Creating encrypted HDL

# 2012.02.04 15:56:39 (*) Done Nios II generation

# 2012.02.04 15:56:40 (*) Running Generator Program for sdram_0

# 2012.02.04 15:56:42 (*) Running Generator Program for pio_0

# 2012.02.04 15:56:43 (*) Running Generator Program for sysid

# 2012.02.04 15:56:44 (*) Running Generator Program for jtag_uart_0

# 2012.02.04 15:56:46 (*) Running Generator Program for epcs_flash_controller_0

# 2012.02.04 15:56:48 (*) Running Generator Program for NIOS_clock_0

# 2012.02.04 15:56:50 (*) Running Generator Program for NIOS_clock_1

# 2012.02.04 15:56:53 (*) Running Generator Program for NIOS_clock_2

# 2012.02.04 15:56:55 (*) Running Generator Program for NIOS_clock_3

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# 2012.02.04 15:56:57 (*) Running Test Generator Program for sdram_0

# 2012.02.04 15:56:58 (*) Making arbitration and system (top) modules.

# 2012.02.04 15:57:08 (*) Generating Quartus symbol for top level: NIOS

# 2012.02.04 15:57:08 (*) Generating Symbol E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS.bsf

# 2012.02.04 15:57:08 (*) Creating command-line system-generation script: E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS_generation_script

# 2012.02.04 15:57:08 (*) Running setup for HDL simulator: modelsim


# 2012.02.04 15:57:09 (*) Completed generation for system: NIOS.
# 2012.02.04 15:57:09 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS.ptf 
  System HDL Model : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS.v 
  System Generation Script : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sdram_test/NIOS_generation_script 

# 2012.02.04 15:57:09 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


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