Altera SOPC Builder Version 11.00 Build 157
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved.


No .sopc_builder configuration file(!)
# 2012.02.06 16:30:16 (*) mk_custom_sdk starting
# 2012.02.06 16:30:16 (*) Reading project E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro.ptf.

# 2012.02.06 16:30:16 (*) Finding all CPUs
# 2012.02.06 16:30:16 (*) Finding all available components
# 2012.02.06 16:30:16 (*) Reading E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/.sopc_builder/install.ptf

# 2012.02.06 16:30:16 (*) Found 63 components

# 2012.02.06 16:30:17 (*) Finding all peripherals

# 2012.02.06 16:30:17 (*) Finding software components

# 2012.02.06 16:30:18 (*) (Legacy SDK Generation Skipped)
# 2012.02.06 16:30:18 (*) (All TCL Script Generation Skipped)
# 2012.02.06 16:30:18 (*) (No Libraries Built)
# 2012.02.06 16:30:18 (*) (Contents Generation Skipped)
# 2012.02.06 16:30:18 (*) mk_custom_sdk finishing

# 2012.02.06 16:30:18 (*) Starting generation for system: base_cro.

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# 2012.02.06 16:30:19 (*) Running Generator Program for cpu_0

# 2012.02.06 16:30:21 (*) Starting Nios II generation
# 2012.02.06 16:30:21 (*)   Checking for plaintext license.
# 2012.02.06 16:30:27 (*)   Plaintext license not found.
# 2012.02.06 16:30:27 (*)   Checking for encrypted license (non-evaluation).
# 2012.02.06 16:30:29 (*)   Encrypted license found.  SOF will not be time-limited.
# 2012.02.06 16:30:29 (*)   Getting CPU configuration settings
# 2012.02.06 16:30:29 (*)   Elaborating CPU configuration settings
# 2012.02.06 16:30:29 (*)   Creating all objects for CPU

# 2012.02.06 16:30:29 (*)     Testbench
# 2012.02.06 16:30:30 (*)     Instruction decoding
# 2012.02.06 16:30:30 (*)       Instruction fields
# 2012.02.06 16:30:30 (*)       Instruction decodes
# 2012.02.06 16:30:31 (*)       Signals for RTL simulation waveforms
# 2012.02.06 16:30:31 (*)       Instruction controls
# 2012.02.06 16:30:31 (*)     Pipeline frontend
# 2012.02.06 16:30:31 (*)     Pipeline backend
# 2012.02.06 16:30:34 (*)   Generating HDL from CPU objects
# 2012.02.06 16:30:38 (*)   Creating encrypted HDL

# 2012.02.06 16:30:39 (*) Done Nios II generation

# 2012.02.06 16:30:40 (*) Running Generator Program for sdram_0

# 2012.02.06 16:30:41 (*) Running Generator Program for sysid_0

# 2012.02.06 16:30:42 (*) Running Generator Program for jtag_uart_0

# 2012.02.06 16:30:43 (*) Running Generator Program for epcs_flash_controller_0

# 2012.02.06 16:30:44 (*) Running Generator Program for LED

# 2012.02.06 16:30:45 (*) Running Generator Program for spi_touch

# 2012.02.06 16:30:46 (*) Running Generator Program for spi_lcd22

# 2012.02.06 16:30:47 (*) Running Generator Program for pc

# 2012.02.06 16:30:48 (*) Running Generator Program for uart_0

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# 2012.02.06 16:30:49 (*) Running Test Generator Program for sdram_0

# 2012.02.06 16:30:50 (*) Making arbitration and system (top) modules.

# 2012.02.06 16:30:56 (*) Generating Quartus symbol for top level: base_cro

# 2012.02.06 16:30:56 (*) Generating Symbol E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro.bsf

# 2012.02.06 16:30:56 (*) Creating command-line system-generation script: E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro_generation_script

# 2012.02.06 16:30:56 (*) Running setup for HDL simulator: modelsim


# 2012.02.06 16:30:56 (*) Completed generation for system: base_cro.
# 2012.02.06 16:30:56 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro.ptf 
  System HDL Model : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro.v 
  System Generation Script : E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/uart_ok/base_cro_generation_script 

# 2012.02.06 16:30:56 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


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