Static Timing Analysis Report

Clock	Domain	Nominal Frequency	Required Frequency	Maximum Frequency
CyILO	CyILO	1.000 kHz	1.000 kHz	N/A
CyIMO	CyIMO	3.000 MHz	3.000 MHz	N/A
CyMASTER_CLK	CyMASTER_CLK	24.000 MHz	24.000 MHz	N/A
CyBUS_CLK	CyMASTER_CLK	24.000 MHz	24.000 MHz	N/A
\CTLREG:Sync:ctrl_reg\/control_0	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_1	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_2	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_3	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_4	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_5	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_7	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\C_DRIVE:Sync:ctrl_reg\/control_0	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\C_DRIVE:Sync:ctrl_reg\/control_2	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_0	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
\A_DRIVE_A:Sync:ctrl_reg\/control_6	CyMASTER_CLK	UNKNOWN	UNKNOWN	N/A
CyPLL_OUT	CyPLL_OUT	24.000 MHz	24.000 MHz	N/A
phi(0)_PAD	phi(0)_PAD	UNKNOWN	UNKNOWN	116.891 MHz

Path Delay Requirement : 10000ns

Source

Destination

FMax

Delay (ns)

Slack (ns)

Violation

Net_20/q

Net_20/main_0

116.891 MHz

8.555

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	Net_20	Net_20/clock_0	Net_20/q	1.250
macrocell9	U(2,4)	1	Net_20	Net_20/q	Net_20/main_0	3.795
macrocell9	U(2,4)	1	Net_20		SETUP	3.510
Clock					Skew	0.000

\APUclkDivider:not_last_reset\/q

Net_20/main_2

132.048 MHz

7.573

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(3,4)	1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/clock_0	\APUclkDivider:not_last_reset\/q	1.250
Route		1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/q	Net_20/main_2	2.792
macrocell9	U(2,4)	1	Net_20		SETUP	3.510
Clock					Skew	0.021

\APUclkDivider:not_last_reset\/q

\APUclkDivider:count_2\/main_1

132.048 MHz

7.573

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(3,4)	1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/clock_0	\APUclkDivider:not_last_reset\/q	1.250
Route		1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/q	\APUclkDivider:count_2\/main_1	2.792
macrocell11	U(2,4)	1	\APUclkDivider:count_2\		SETUP	3.510
Clock					Skew	0.021

\APUclkDivider:not_last_reset\/q

\APUclkDivider:count_1\/main_1

132.048 MHz

7.573

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(3,4)	1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/clock_0	\APUclkDivider:not_last_reset\/q	1.250
Route		1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/q	\APUclkDivider:count_1\/main_1	2.792
macrocell12	U(2,4)	1	\APUclkDivider:count_1\		SETUP	3.510
Clock					Skew	0.021

\APUclkDivider:not_last_reset\/q

\APUclkDivider:count_0\/main_1

132.048 MHz

7.573

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(3,4)	1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/clock_0	\APUclkDivider:not_last_reset\/q	1.250
Route		1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/q	\APUclkDivider:count_0\/main_1	2.792
macrocell13	U(2,4)	1	\APUclkDivider:count_0\		SETUP	3.510
Clock					Skew	0.021

\APUclkDivider:count_0\/q

\APUclkDivider:count_0\/main_2

132.433 MHz

7.551

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_0\/main_2	2.791
macrocell13	U(2,4)	1	\APUclkDivider:count_0\		SETUP	3.510
Clock					Skew	0.000

\APUclkDivider:count_0\/q

Net_20/main_5

132.626 MHz

7.540

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	Net_20/main_5	2.780
macrocell9	U(2,4)	1	Net_20		SETUP	3.510
Clock					Skew	0.000

\APUclkDivider:count_0\/q

\APUclkDivider:count_2\/main_4

132.626 MHz

7.540

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_2\/main_4	2.780
macrocell11	U(2,4)	1	\APUclkDivider:count_2\		SETUP	3.510
Clock					Skew	0.000

\APUclkDivider:count_0\/q

\APUclkDivider:count_1\/main_3

132.626 MHz

7.540

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_1\/main_3	2.780
macrocell12	U(2,4)	1	\APUclkDivider:count_1\		SETUP	3.510
Clock					Skew	0.000

\APUclkDivider:count_2\/q

Net_20/main_3

141.663 MHz

7.059

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell11	U(2,4)	1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/clock_0	\APUclkDivider:count_2\/q	1.250
Route		1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/q	Net_20/main_3	2.299
macrocell9	U(2,4)	1	Net_20		SETUP	3.510
Clock					Skew	0.000

+ Hold Subsection

+ Source Clock : phi(0)_PAD : Positive edge

+ Destination Clock : phi(0)_PAD : Positive edge

Source

Destination

Slack (ns)

Violation

\APUclkDivider:count_1\/q

Net_20/main_4

3.539

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell12	U(2,4)	1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/clock_0	\APUclkDivider:count_1\/q	1.250
Route		1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/q	Net_20/main_4	2.289
macrocell9	U(2,4)	1	Net_20		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_1\/q

\APUclkDivider:count_2\/main_3

3.539

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell12	U(2,4)	1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/clock_0	\APUclkDivider:count_1\/q	1.250
Route		1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/q	\APUclkDivider:count_2\/main_3	2.289
macrocell11	U(2,4)	1	\APUclkDivider:count_2\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_1\/q

\APUclkDivider:count_1\/main_2

3.539

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell12	U(2,4)	1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/clock_0	\APUclkDivider:count_1\/q	1.250
macrocell12	U(2,4)	1	\APUclkDivider:count_1\	\APUclkDivider:count_1\/q	\APUclkDivider:count_1\/main_2	2.289
macrocell12	U(2,4)	1	\APUclkDivider:count_1\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_2\/q

Net_20/main_3

3.549

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell11	U(2,4)	1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/clock_0	\APUclkDivider:count_2\/q	1.250
Route		1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/q	Net_20/main_3	2.299
macrocell9	U(2,4)	1	Net_20		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_2\/q

\APUclkDivider:count_2\/main_2

3.549

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell11	U(2,4)	1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/clock_0	\APUclkDivider:count_2\/q	1.250
macrocell11	U(2,4)	1	\APUclkDivider:count_2\	\APUclkDivider:count_2\/q	\APUclkDivider:count_2\/main_2	2.299
macrocell11	U(2,4)	1	\APUclkDivider:count_2\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_0\/q

Net_20/main_5

4.030

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	Net_20/main_5	2.780
macrocell9	U(2,4)	1	Net_20		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_0\/q

\APUclkDivider:count_2\/main_4

4.030

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_2\/main_4	2.780
macrocell11	U(2,4)	1	\APUclkDivider:count_2\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_0\/q

\APUclkDivider:count_1\/main_3

4.030

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
Route		1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_1\/main_3	2.780
macrocell12	U(2,4)	1	\APUclkDivider:count_1\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:count_0\/q

\APUclkDivider:count_0\/main_2

4.041

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/clock_0	\APUclkDivider:count_0\/q	1.250
macrocell13	U(2,4)	1	\APUclkDivider:count_0\	\APUclkDivider:count_0\/q	\APUclkDivider:count_0\/main_2	2.791
macrocell13	U(2,4)	1	\APUclkDivider:count_0\		HOLD	0.000
Clock					Skew	0.000

\APUclkDivider:not_last_reset\/q

Net_20/main_2

4.063

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(3,4)	1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/clock_0	\APUclkDivider:not_last_reset\/q	1.250
Route		1	\APUclkDivider:not_last_reset\	\APUclkDivider:not_last_reset\/q	Net_20/main_2	2.792
macrocell9	U(2,4)	1	Net_20		HOLD	0.000
Clock					Skew	0.021

+ Input To Output Section

Source

Destination

Delay (ns)

A5(0)_PAD:in

nINT0(0)_PAD

50.698

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A5(0)_PAD:in	A5(0)_PAD:in	A5(0)_PAD:in	0.000
Route		1	A5(0)_PAD	A5(0)_PAD:in	A5(0)/pad_in	0.000
iocell31	P2[4]	1	A5(0)	A5(0)/pad_in	A5(0)/fb	7.454
Route		1	net_AB_5	A5(0)/fb	Net_499_split/main_5	11.060
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_5	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A0(0)_PAD:in

nINT0(0)_PAD

49.480

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A0(0)_PAD:in	A0(0)_PAD:in	A0(0)_PAD:in	0.000
Route		1	A0(0)_PAD	A0(0)_PAD:in	A0(0)/pad_in	0.000
iocell33	P6[0]	1	A0(0)	A0(0)/pad_in	A0(0)/fb	7.816
Route		1	net_AB_0	A0(0)/fb	Net_499_split/main_8	9.480
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_8	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A7(0)_PAD:in

nINT0(0)_PAD

49.118

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A7(0)_PAD:in	A7(0)_PAD:in	A7(0)_PAD:in	0.000
Route		1	A7(0)_PAD	A7(0)_PAD:in	A7(0)/pad_in	0.000
iocell32	P2[5]	1	A7(0)	A7(0)/pad_in	A7(0)/fb	7.735
Route		1	net_AB_7	A7(0)/fb	Net_499_split/main_6	9.199
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_6	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A6(0)_PAD:in

nINT0(0)_PAD

48.356

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A6(0)_PAD:in	A6(0)_PAD:in	A6(0)_PAD:in	0.000
Route		1	A6(0)_PAD	A6(0)_PAD:in	A6(0)/pad_in	0.000
iocell36	P0[5]	1	A6(0)	A6(0)/pad_in	A6(0)/fb	8.264
Route		1	net_AB_6	A6(0)/fb	Net_499_split/main_10	7.908
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_10	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A3(0)_PAD:in

nINT0(0)_PAD

47.929

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A3(0)_PAD:in	A3(0)_PAD:in	A3(0)_PAD:in	0.000
Route		1	A3(0)_PAD	A3(0)_PAD:in	A3(0)/pad_in	0.000
iocell30	P15[0]	1	A3(0)	A3(0)/pad_in	A3(0)/fb	6.334
Route		1	net_AB_3	A3(0)/fb	Net_499_split/main_3	9.411
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_3	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

nIOE(0)_PAD:in

nINT0(0)_PAD

47.171

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	nIOE(0)_PAD:in	nIOE(0)_PAD:in	nIOE(0)_PAD:in	0.000
Route		1	nIOE(0)_PAD	nIOE(0)_PAD:in	nIOE(0)/pad_in	0.000
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pad_in	nIOE(0)/fb	7.958
Route		1	net_nIOE	nIOE(0)/fb	Net_499_split/main_7	7.029
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_7	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A1(0)_PAD:in

nINT0(0)_PAD

47.110

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A1(0)_PAD:in	A1(0)_PAD:in	A1(0)_PAD:in	0.000
Route		1	A1(0)_PAD	A1(0)_PAD:in	A1(0)/pad_in	0.000
iocell29	P12[2]	1	A1(0)	A1(0)/pad_in	A1(0)/fb	7.315
Route		1	net_AB_1	A1(0)/fb	Net_499_split/main_1	7.611
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_1	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

nRD(0)_PAD:in

nINT0(0)_PAD

46.500

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	nRD(0)_PAD:in	nRD(0)_PAD:in	nRD(0)_PAD:in	0.000
Route		1	nRD(0)_PAD	nRD(0)_PAD:in	nRD(0)/pad_in	0.000
iocell12	P3[5]	1	nRD(0)	nRD(0)/pad_in	nRD(0)/fb	6.774
Route		1	net_nRD	nRD(0)/fb	Net_499_split/main_9	7.542
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_9	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A2(0)_PAD:in

nINT0(0)_PAD

45.292

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A2(0)_PAD:in	A2(0)_PAD:in	A2(0)_PAD:in	0.000
Route		1	A2(0)_PAD	A2(0)_PAD:in	A2(0)/pad_in	0.000
iocell34	P3[4]	1	A2(0)	A2(0)/pad_in	A2(0)/fb	6.038
Route		1	net_AB_2	A2(0)/fb	Net_499_split/main_2	7.070
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_2	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

A4(0)_PAD:in

nINT0(0)_PAD

45.177

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A4(0)_PAD:in	A4(0)_PAD:in	A4(0)_PAD:in	0.000
Route		1	A4(0)_PAD	A4(0)_PAD:in	A4(0)/pad_in	0.000
iocell35	P15[2]	1	A4(0)	A4(0)/pad_in	A4(0)/fb	6.653
Route		1	net_AB_4	A4(0)/fb	Net_499_split/main_4	6.340
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_4	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000

nME(0)_PAD:in

nRAMCS1(0)_PAD

42.947

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	nME(0)_PAD:in	nME(0)_PAD:in	nME(0)_PAD:in	0.000
Route		1	nME(0)_PAD	nME(0)_PAD:in	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_102/main_1	8.862
macrocell6	U(3,3)	1	Net_102	Net_102/main_1	Net_102/q	3.350
Route		1	Net_102	Net_102/q	nRAMCS1(0)/pin_input	8.022
iocell24	P3[1]	1	nRAMCS1(0)	nRAMCS1(0)/pin_input	nRAMCS1(0)/pad_out	14.979
Route		1	nRAMCS1(0)_PAD	nRAMCS1(0)/pad_out	nRAMCS1(0)_PAD	0.000

A19(0)_PAD:in

nRAMCS1(0)_PAD

39.956

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A19(0)_PAD:in	A19(0)_PAD:in	A19(0)_PAD:in	0.000
Route		1	A19(0)_PAD	A19(0)_PAD:in	A19(0)/pad_in	0.000
iocell48	P15[3]	1	A19(0)	A19(0)/pad_in	A19(0)/fb	6.523
Route		1	net_AB_19	A19(0)/fb	Net_102/main_0	7.082
macrocell6	U(3,3)	1	Net_102	Net_102/main_0	Net_102/q	3.350
Route		1	Net_102	Net_102/q	nRAMCS1(0)/pin_input	8.022
iocell24	P3[1]	1	nRAMCS1(0)	nRAMCS1(0)/pin_input	nRAMCS1(0)/pad_out	14.979
Route		1	nRAMCS1(0)_PAD	nRAMCS1(0)/pad_out	nRAMCS1(0)_PAD	0.000

nME(0)_PAD:in

nRAMCS0(0)_PAD

43.248

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	nME(0)_PAD:in	nME(0)_PAD:in	nME(0)_PAD:in	0.000
Route		1	nME(0)_PAD	nME(0)_PAD:in	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_99/main_2	8.864
macrocell5	U(2,3)	1	Net_99	Net_99/main_2	Net_99/q	3.350
Route		1	Net_99	Net_99/q	nRAMCS0(0)/pin_input	7.513
iocell25	P2[2]	1	nRAMCS0(0)	nRAMCS0(0)/pin_input	nRAMCS0(0)/pad_out	15.787
Route		1	nRAMCS0(0)_PAD	nRAMCS0(0)/pad_out	nRAMCS0(0)_PAD	0.000

A19(0)_PAD:in

nRAMCS0(0)_PAD

40.261

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A19(0)_PAD:in	A19(0)_PAD:in	A19(0)_PAD:in	0.000
Route		1	A19(0)_PAD	A19(0)_PAD:in	A19(0)/pad_in	0.000
iocell48	P15[3]	1	A19(0)	A19(0)/pad_in	A19(0)/fb	6.523
Route		1	net_AB_19	A19(0)/fb	Net_99/main_1	7.088
macrocell5	U(2,3)	1	Net_99	Net_99/main_1	Net_99/q	3.350
Route		1	Net_99	Net_99/q	nRAMCS0(0)/pin_input	7.513
iocell25	P2[2]	1	nRAMCS0(0)	nRAMCS0(0)/pin_input	nRAMCS0(0)/pad_out	15.787
Route		1	nRAMCS0(0)_PAD	nRAMCS0(0)/pad_out	nRAMCS0(0)_PAD	0.000

nME(0)_PAD:in

nROMCS(0)_PAD

38.885

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	nME(0)_PAD:in	nME(0)_PAD:in	nME(0)_PAD:in	0.000
Route		1	nME(0)_PAD	nME(0)_PAD:in	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_94/main_2	7.030
macrocell4	U(3,1)	1	Net_94	Net_94/main_2	Net_94/q	3.350
Route		1	Net_94	Net_94/q	nROMCS(0)/pin_input	6.342
iocell26	P15[1]	1	nROMCS(0)	nROMCS(0)/pin_input	nROMCS(0)/pad_out	14.429
Route		1	nROMCS(0)_PAD	nROMCS(0)/pad_out	nROMCS(0)_PAD	0.000

A19(0)_PAD:in

nROMCS(0)_PAD

35.943

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
URSO180GLUESoC2		1	A19(0)_PAD:in	A19(0)_PAD:in	A19(0)_PAD:in	0.000
Route		1	A19(0)_PAD	A19(0)_PAD:in	A19(0)/pad_in	0.000
iocell48	P15[3]	1	A19(0)	A19(0)/pad_in	A19(0)/fb	6.523
Route		1	net_AB_19	A19(0)/fb	Net_94/main_1	5.299
macrocell4	U(3,1)	1	Net_94	Net_94/main_1	Net_94/q	3.350
Route		1	Net_94	Net_94/q	nROMCS(0)/pin_input	6.342
iocell26	P15[1]	1	nROMCS(0)	nROMCS(0)/pin_input	nROMCS(0)/pad_out	14.429
Route		1	nROMCS(0)_PAD	nROMCS(0)/pad_out	nROMCS(0)_PAD	0.000

+ Input To Clock Section

+ phi(0)_PAD

Source

Destination

Delay (ns)

nRESET(0)_PAD

\APUclkDivider:count_0\/main_0

4.264

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
Route		1	nRESET(0)_PAD	nRESET(0)_PAD	nRESET(0)/pad_in	0.000
iocell5	P2[3]	1	nRESET(0)	nRESET(0)/pad_in	nRESET(0)/fb	7.659
Route		1	Net_30	nRESET(0)/fb	\APUclkDivider:count_0\/main_0	6.928
macrocell13	U(2,4)	1	\APUclkDivider:count_0\		SETUP	3.510
Clock					Clock path delay	-13.833

+ Clock To Output Section

+ CyBUS_CLK

Source

Destination

Delay (ns)

\C_DRIVE:Sync:ctrl_reg\/control_3

nINT0(0)_PAD

70.095

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_3	2.050
Route		1	drive_nRD	\C_DRIVE:Sync:ctrl_reg\/control_3	nRD(0)/pin_input	6.207
iocell12	P3[5]	1	nRD(0)	nRD(0)/pin_input	nRD(0)/pad_out	15.338
iocell12	P3[5]	1	nRD(0)	nRD(0)/pad_out	nRD(0)/pad_in	0.000
iocell12	P3[5]	1	nRD(0)	nRD(0)/pad_in	nRD(0)/fb	6.774
Route		1	net_nRD	nRD(0)/fb	Net_499_split/main_9	7.542
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_9	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_1

nRAMCS0(0)_PAD

68.239

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_nME	\C_DRIVE:Sync:ctrl_reg\/control_1	nME(0)/pin_input	7.290
iocell23	P5[2]	1	nME(0)	nME(0)/pin_input	nME(0)/pad_out	15.651
iocell23	P5[2]	1	nME(0)	nME(0)/pad_out	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_99/main_2	8.864
macrocell5	U(2,3)	1	Net_99	Net_99/main_2	Net_99/q	3.350
Route		1	Net_99	Net_99/q	nRAMCS0(0)/pin_input	7.513
iocell25	P2[2]	1	nRAMCS0(0)	nRAMCS0(0)/pin_input	nRAMCS0(0)/pad_out	15.787
Route		1	nRAMCS0(0)_PAD	nRAMCS0(0)/pad_out	nRAMCS0(0)_PAD	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_1

nRAMCS1(0)_PAD

67.938

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_nME	\C_DRIVE:Sync:ctrl_reg\/control_1	nME(0)/pin_input	7.290
iocell23	P5[2]	1	nME(0)	nME(0)/pin_input	nME(0)/pad_out	15.651
iocell23	P5[2]	1	nME(0)	nME(0)/pad_out	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_102/main_1	8.862
macrocell6	U(3,3)	1	Net_102	Net_102/main_1	Net_102/q	3.350
Route		1	Net_102	Net_102/q	nRAMCS1(0)/pin_input	8.022
iocell24	P3[1]	1	nRAMCS1(0)	nRAMCS1(0)/pin_input	nRAMCS1(0)/pad_out	14.979
Route		1	nRAMCS1(0)_PAD	nRAMCS1(0)/pad_out	nRAMCS1(0)_PAD	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_1

nROMCS(0)_PAD

63.876

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_nME	\C_DRIVE:Sync:ctrl_reg\/control_1	nME(0)/pin_input	7.290
iocell23	P5[2]	1	nME(0)	nME(0)/pin_input	nME(0)/pad_out	15.651
iocell23	P5[2]	1	nME(0)	nME(0)/pad_out	nME(0)/pad_in	0.000
iocell23	P5[2]	1	nME(0)	nME(0)/pad_in	nME(0)/fb	7.734
Route		1	net_nME	nME(0)/fb	Net_94/main_2	7.030
macrocell4	U(3,1)	1	Net_94	Net_94/main_2	Net_94/q	3.350
Route		1	Net_94	Net_94/q	nROMCS(0)/pin_input	6.342
iocell26	P15[1]	1	nROMCS(0)	nROMCS(0)/pin_input	nROMCS(0)/pad_out	14.429
Route		1	nROMCS(0)_PAD	nROMCS(0)/pad_out	nROMCS(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_C:Sync:ctrl_reg\/control_0

A16(0)_PAD:out

26.247

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell4	U(3,2)	1	\A_DRIVE_C:Sync:ctrl_reg\	\A_DRIVE_C:Sync:ctrl_reg\/busclk	\A_DRIVE_C:Sync:ctrl_reg\/control_0	2.050
Route		1	drive_AB_16	\A_DRIVE_C:Sync:ctrl_reg\/control_0	A16(0)/pin_input	8.221
iocell45	P4[6]	1	A16(0)	A16(0)/pin_input	A16(0)/pad_out	15.976
Route		1	A16(0)_PAD	A16(0)/pad_out	A16(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_C:Sync:ctrl_reg\/control_1

A17(0)_PAD:out

26.209

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell4	U(3,2)	1	\A_DRIVE_C:Sync:ctrl_reg\	\A_DRIVE_C:Sync:ctrl_reg\/busclk	\A_DRIVE_C:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_AB_17	\A_DRIVE_C:Sync:ctrl_reg\/control_1	A17(0)/pin_input	8.268
iocell46	P2[1]	1	A17(0)	A17(0)/pin_input	A17(0)/pad_out	15.891
Route		1	A17(0)_PAD	A17(0)/pad_out	A17(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_5

DB5(0)_PAD:out

25.161

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_5	2.050
Route		1	Net_332	\TO_MPU_REG:Sync:ctrl_reg\/control_5	DB5(0)/pin_input	8.116
iocell20	P3[2]	1	DB5(0)	DB5(0)/pin_input	DB5(0)/pad_out	14.995
Route		1	DB5(0)_PAD	DB5(0)/pad_out	DB5(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_0

DB0(0)_PAD:out

25.100

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_0	2.050
Route		1	Net_300	\TO_MPU_REG:Sync:ctrl_reg\/control_0	DB0(0)/pin_input	7.125
iocell22	P15[5]	1	DB0(0)	DB0(0)/pin_input	DB0(0)/pad_out	15.925
Route		1	DB0(0)_PAD	DB0(0)/pad_out	DB0(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_1

DB1(0)_PAD:out

25.057

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_1	2.050
Route		1	Net_324	\TO_MPU_REG:Sync:ctrl_reg\/control_1	DB1(0)/pin_input	8.127
iocell13	P6[1]	1	DB1(0)	DB1(0)/pin_input	DB1(0)/pad_out	14.880
Route		1	DB1(0)_PAD	DB1(0)/pad_out	DB1(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_1

nME(0)_PAD:out

24.991

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_nME	\C_DRIVE:Sync:ctrl_reg\/control_1	nME(0)/pin_input	7.290
iocell23	P5[2]	1	nME(0)	nME(0)/pin_input	nME(0)/pad_out	15.651
Route		1	nME(0)_PAD	nME(0)/pad_out	nME(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_0

A8(0)_PAD:out

24.251

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_0	2.050
Route		1	drive_AB_8	\A_DRIVE_B:Sync:ctrl_reg\/control_0	A8(0)/pin_input	6.399
iocell41	P0[1]	1	A8(0)	A8(0)/pin_input	A8(0)/pad_out	15.802
Route		1	A8(0)_PAD	A8(0)/pad_out	A8(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_7

DB7(0)_PAD:out

24.167

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_7	2.050
Route		1	Net_336	\TO_MPU_REG:Sync:ctrl_reg\/control_7	DB7(0)/pin_input	7.066
iocell19	P4[0]	1	DB7(0)	DB7(0)/pin_input	DB7(0)/pad_out	15.051
Route		1	DB7(0)_PAD	DB7(0)/pad_out	DB7(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_6

DB6(0)_PAD:out

24.140

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_6	2.050
Route		1	Net_320	\TO_MPU_REG:Sync:ctrl_reg\/control_6	DB6(0)/pin_input	6.743
iocell16	P4[5]	1	DB6(0)	DB6(0)/pin_input	DB6(0)/pad_out	15.347
Route		1	DB6(0)_PAD	DB6(0)/pad_out	DB6(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_C:Sync:ctrl_reg\/control_3

A19(0)_PAD:out

24.081

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell4	U(3,2)	1	\A_DRIVE_C:Sync:ctrl_reg\	\A_DRIVE_C:Sync:ctrl_reg\/busclk	\A_DRIVE_C:Sync:ctrl_reg\/control_3	2.050
Route		1	drive_AB_19	\A_DRIVE_C:Sync:ctrl_reg\/control_3	A19(0)/pin_input	6.545
iocell48	P15[3]	1	A19(0)	A19(0)/pin_input	A19(0)/pad_out	15.486
Route		1	A19(0)_PAD	A19(0)/pad_out	A19(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_1

A9(0)_PAD:out

24.079

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_1	2.050
Route		1	drive_AB_9	\A_DRIVE_B:Sync:ctrl_reg\/control_1	A9(0)/pin_input	5.833
iocell37	P12[3]	1	A9(0)	A9(0)/pin_input	A9(0)/pad_out	16.196
Route		1	A9(0)_PAD	A9(0)/pad_out	A9(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_4

DB4(0)_PAD:out

23.892

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_4	2.050
Route		1	Net_316	\TO_MPU_REG:Sync:ctrl_reg\/control_4	DB4(0)/pin_input	6.620
iocell17	P4[7]	1	DB4(0)	DB4(0)/pin_input	DB4(0)/pad_out	15.222
Route		1	DB4(0)_PAD	DB4(0)/pad_out	DB4(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_5

A13(0)_PAD:out

23.880

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_5	2.050
Route		1	drive_AB_13	\A_DRIVE_B:Sync:ctrl_reg\/control_5	A13(0)/pin_input	6.719
iocell39	P4[2]	1	A13(0)	A13(0)/pin_input	A13(0)/pad_out	15.111
Route		1	A13(0)_PAD	A13(0)/pad_out	A13(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_3

nRD(0)_PAD:out

23.595

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	\C_DRIVE:Sync:ctrl_reg\/busclk	\C_DRIVE:Sync:ctrl_reg\/control_3	2.050
Route		1	drive_nRD	\C_DRIVE:Sync:ctrl_reg\/control_3	nRD(0)/pin_input	6.207
iocell12	P3[5]	1	nRD(0)	nRD(0)/pin_input	nRD(0)/pad_out	15.338
Route		1	nRD(0)_PAD	nRD(0)/pad_out	nRD(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_4

A12(0)_PAD:out

23.490

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_4	2.050
Route		1	drive_AB_12	\A_DRIVE_B:Sync:ctrl_reg\/control_4	A12(0)/pin_input	6.347
iocell43	P4[3]	1	A12(0)	A12(0)/pin_input	A12(0)/pad_out	15.093
Route		1	A12(0)_PAD	A12(0)/pad_out	A12(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_2

DB2(0)_PAD:out

23.436

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_2	2.050
Route		1	Net_312	\TO_MPU_REG:Sync:ctrl_reg\/control_2	DB2(0)/pin_input	5.825
iocell18	P0[6]	1	DB2(0)	DB2(0)/pin_input	DB2(0)/pad_out	15.561
Route		1	DB2(0)_PAD	DB2(0)/pad_out	DB2(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\TO_MPU_REG:Sync:ctrl_reg\/control_3

DB3(0)_PAD:out

23.268

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell1	U(3,3)	1	\TO_MPU_REG:Sync:ctrl_reg\	\TO_MPU_REG:Sync:ctrl_reg\/busclk	\TO_MPU_REG:Sync:ctrl_reg\/control_3	2.050
Route		1	Net_328	\TO_MPU_REG:Sync:ctrl_reg\/control_3	DB3(0)/pin_input	5.759
iocell21	P0[2]	1	DB3(0)	DB3(0)/pin_input	DB3(0)/pad_out	15.459
Route		1	DB3(0)_PAD	DB3(0)/pad_out	DB3(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_C:Sync:ctrl_reg\/control_2

A18(0)_PAD:out

23.213

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell4	U(3,2)	1	\A_DRIVE_C:Sync:ctrl_reg\	\A_DRIVE_C:Sync:ctrl_reg\/busclk	\A_DRIVE_C:Sync:ctrl_reg\/control_2	2.050
Route		1	drive_AB_18	\A_DRIVE_C:Sync:ctrl_reg\/control_2	A18(0)/pin_input	6.572
iocell47	P3[3]	1	A18(0)	A18(0)/pin_input	A18(0)/pad_out	14.591
Route		1	A18(0)_PAD	A18(0)/pad_out	A18(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_7

A15(0)_PAD:out

23.022

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_7	2.050
Route		1	drive_AB_15	\A_DRIVE_B:Sync:ctrl_reg\/control_7	A15(0)/pin_input	5.477
iocell40	P0[7]	1	A15(0)	A15(0)/pin_input	A15(0)/pad_out	15.495
Route		1	A15(0)_PAD	A15(0)/pad_out	A15(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_2

A10(0)_PAD:out

22.918

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_2	2.050
Route		1	drive_AB_10	\A_DRIVE_B:Sync:ctrl_reg\/control_2	A10(0)/pin_input	5.884
iocell42	P4[1]	1	A10(0)	A10(0)/pin_input	A10(0)/pad_out	14.984
Route		1	A10(0)_PAD	A10(0)/pad_out	A10(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_3

A11(0)_PAD:out

22.704

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_3	2.050
Route		1	drive_AB_11	\A_DRIVE_B:Sync:ctrl_reg\/control_3	A11(0)/pin_input	5.403
iocell38	P0[0]	1	A11(0)	A11(0)/pin_input	A11(0)/pad_out	15.251
Route		1	A11(0)_PAD	A11(0)/pad_out	A11(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_B:Sync:ctrl_reg\/control_6

A14(0)_PAD:out

22.421

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell3	U(3,4)	1	\A_DRIVE_B:Sync:ctrl_reg\	\A_DRIVE_B:Sync:ctrl_reg\/busclk	\A_DRIVE_B:Sync:ctrl_reg\/control_6	2.050
Route		1	drive_AB_14	\A_DRIVE_B:Sync:ctrl_reg\/control_6	A14(0)/pin_input	5.491
iocell44	P0[4]	1	A14(0)	A14(0)/pin_input	A14(0)/pad_out	14.880
Route		1	A14(0)_PAD	A14(0)/pad_out	A14(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_0

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

74.050

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_AB_0	\A_DRIVE_A:Sync:ctrl_reg\/control_0	A0(0)/pin_input	9.656
iocell33	P6[0]	1	A0(0)	A0(0)/pin_input	A0(0)/pad_out	14.914
iocell33	P6[0]	1	A0(0)	A0(0)/pad_out	A0(0)/pad_in	0.000
iocell33	P6[0]	1	A0(0)	A0(0)/pad_in	A0(0)/fb	7.816
Route		1	net_AB_0	A0(0)/fb	Net_499_split/main_8	9.480
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_8	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

74.050

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_AB_0	\A_DRIVE_A:Sync:ctrl_reg\/control_0	A0(0)/pin_input	9.656
iocell33	P6[0]	1	A0(0)	A0(0)/pin_input	A0(0)/pad_out	14.914
iocell33	P6[0]	1	A0(0)	A0(0)/pad_out	A0(0)/pad_in	0.000
iocell33	P6[0]	1	A0(0)	A0(0)/pad_in	A0(0)/fb	7.816
Route		1	net_AB_0	A0(0)/fb	Net_499_split/main_8	9.480
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_8	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_0

A0(0)_PAD:out

24.570

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_AB_0	\A_DRIVE_A:Sync:ctrl_reg\/control_0	A0(0)/pin_input	9.656
iocell33	P6[0]	1	A0(0)	A0(0)/pin_input	A0(0)/pad_out	14.914
Route		1	A0(0)_PAD	A0(0)/pad_out	A0(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_0

A0(0)_PAD:out

24.570

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_AB_0	\A_DRIVE_A:Sync:ctrl_reg\/control_0	A0(0)/pin_input	9.656
iocell33	P6[0]	1	A0(0)	A0(0)/pin_input	A0(0)/pad_out	14.914
Route		1	A0(0)_PAD	A0(0)/pad_out	A0(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_1

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_1

nINT0(0)_PAD

68.264

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_1	0.000
Route		1	drive_AB_1	\A_DRIVE_A:Sync:ctrl_reg\/control_1	A1(0)/pin_input	5.488
iocell29	P12[2]	1	A1(0)	A1(0)/pin_input	A1(0)/pad_out	15.666
iocell29	P12[2]	1	A1(0)	A1(0)/pad_out	A1(0)/pad_in	0.000
iocell29	P12[2]	1	A1(0)	A1(0)/pad_in	A1(0)/fb	7.315
Route		1	net_AB_1	A1(0)/fb	Net_499_split/main_1	7.611
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_1	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_1

nINT0(0)_PAD

68.264

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_1	0.000
Route		1	drive_AB_1	\A_DRIVE_A:Sync:ctrl_reg\/control_1	A1(0)/pin_input	5.488
iocell29	P12[2]	1	A1(0)	A1(0)/pin_input	A1(0)/pad_out	15.666
iocell29	P12[2]	1	A1(0)	A1(0)/pad_out	A1(0)/pad_in	0.000
iocell29	P12[2]	1	A1(0)	A1(0)/pad_in	A1(0)/fb	7.315
Route		1	net_AB_1	A1(0)/fb	Net_499_split/main_1	7.611
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_1	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_1

A1(0)_PAD:out

21.154

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_1	0.000
Route		1	drive_AB_1	\A_DRIVE_A:Sync:ctrl_reg\/control_1	A1(0)/pin_input	5.488
iocell29	P12[2]	1	A1(0)	A1(0)/pin_input	A1(0)/pad_out	15.666
Route		1	A1(0)_PAD	A1(0)/pad_out	A1(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_1

A1(0)_PAD:out

21.154

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_1	0.000
Route		1	drive_AB_1	\A_DRIVE_A:Sync:ctrl_reg\/control_1	A1(0)/pin_input	5.488
iocell29	P12[2]	1	A1(0)	A1(0)/pin_input	A1(0)/pad_out	15.666
Route		1	A1(0)_PAD	A1(0)/pad_out	A1(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_2

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_2

nINT0(0)_PAD

66.895

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_AB_2	\A_DRIVE_A:Sync:ctrl_reg\/control_2	A2(0)/pin_input	6.616
iocell34	P3[4]	1	A2(0)	A2(0)/pin_input	A2(0)/pad_out	14.987
iocell34	P3[4]	1	A2(0)	A2(0)/pad_out	A2(0)/pad_in	0.000
iocell34	P3[4]	1	A2(0)	A2(0)/pad_in	A2(0)/fb	6.038
Route		1	net_AB_2	A2(0)/fb	Net_499_split/main_2	7.070
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_2	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_2

nINT0(0)_PAD

66.895

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_AB_2	\A_DRIVE_A:Sync:ctrl_reg\/control_2	A2(0)/pin_input	6.616
iocell34	P3[4]	1	A2(0)	A2(0)/pin_input	A2(0)/pad_out	14.987
iocell34	P3[4]	1	A2(0)	A2(0)/pad_out	A2(0)/pad_in	0.000
iocell34	P3[4]	1	A2(0)	A2(0)/pad_in	A2(0)/fb	6.038
Route		1	net_AB_2	A2(0)/fb	Net_499_split/main_2	7.070
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_2	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_2

A2(0)_PAD:out

21.603

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_AB_2	\A_DRIVE_A:Sync:ctrl_reg\/control_2	A2(0)/pin_input	6.616
iocell34	P3[4]	1	A2(0)	A2(0)/pin_input	A2(0)/pad_out	14.987
Route		1	A2(0)_PAD	A2(0)/pad_out	A2(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_2

A2(0)_PAD:out

21.603

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_AB_2	\A_DRIVE_A:Sync:ctrl_reg\/control_2	A2(0)/pin_input	6.616
iocell34	P3[4]	1	A2(0)	A2(0)/pin_input	A2(0)/pad_out	14.987
Route		1	A2(0)_PAD	A2(0)/pad_out	A2(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_3

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_3

nINT0(0)_PAD

67.702

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_3	0.000
Route		1	drive_AB_3	\A_DRIVE_A:Sync:ctrl_reg\/control_3	A3(0)/pin_input	5.518
iocell30	P15[0]	1	A3(0)	A3(0)/pin_input	A3(0)/pad_out	14.255
iocell30	P15[0]	1	A3(0)	A3(0)/pad_out	A3(0)/pad_in	0.000
iocell30	P15[0]	1	A3(0)	A3(0)/pad_in	A3(0)/fb	6.334
Route		1	net_AB_3	A3(0)/fb	Net_499_split/main_3	9.411
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_3	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_3

nINT0(0)_PAD

67.702

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_3	0.000
Route		1	drive_AB_3	\A_DRIVE_A:Sync:ctrl_reg\/control_3	A3(0)/pin_input	5.518
iocell30	P15[0]	1	A3(0)	A3(0)/pin_input	A3(0)/pad_out	14.255
iocell30	P15[0]	1	A3(0)	A3(0)/pad_out	A3(0)/pad_in	0.000
iocell30	P15[0]	1	A3(0)	A3(0)/pad_in	A3(0)/fb	6.334
Route		1	net_AB_3	A3(0)/fb	Net_499_split/main_3	9.411
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_3	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_3

A3(0)_PAD:out

19.773

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_3	0.000
Route		1	drive_AB_3	\A_DRIVE_A:Sync:ctrl_reg\/control_3	A3(0)/pin_input	5.518
iocell30	P15[0]	1	A3(0)	A3(0)/pin_input	A3(0)/pad_out	14.255
Route		1	A3(0)_PAD	A3(0)/pad_out	A3(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_3

A3(0)_PAD:out

19.773

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_3	0.000
Route		1	drive_AB_3	\A_DRIVE_A:Sync:ctrl_reg\/control_3	A3(0)/pin_input	5.518
iocell30	P15[0]	1	A3(0)	A3(0)/pin_input	A3(0)/pad_out	14.255
Route		1	A3(0)_PAD	A3(0)/pad_out	A3(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_4

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_4

nINT0(0)_PAD

66.544

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_4	0.000
Route		1	drive_AB_4	\A_DRIVE_A:Sync:ctrl_reg\/control_4	A4(0)/pin_input	6.263
iocell35	P15[2]	1	A4(0)	A4(0)/pin_input	A4(0)/pad_out	15.104
iocell35	P15[2]	1	A4(0)	A4(0)/pad_out	A4(0)/pad_in	0.000
iocell35	P15[2]	1	A4(0)	A4(0)/pad_in	A4(0)/fb	6.653
Route		1	net_AB_4	A4(0)/fb	Net_499_split/main_4	6.340
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_4	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_4

nINT0(0)_PAD

66.544

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_4	0.000
Route		1	drive_AB_4	\A_DRIVE_A:Sync:ctrl_reg\/control_4	A4(0)/pin_input	6.263
iocell35	P15[2]	1	A4(0)	A4(0)/pin_input	A4(0)/pad_out	15.104
iocell35	P15[2]	1	A4(0)	A4(0)/pad_out	A4(0)/pad_in	0.000
iocell35	P15[2]	1	A4(0)	A4(0)/pad_in	A4(0)/fb	6.653
Route		1	net_AB_4	A4(0)/fb	Net_499_split/main_4	6.340
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_4	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_4

A4(0)_PAD:out

21.367

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_4	0.000
Route		1	drive_AB_4	\A_DRIVE_A:Sync:ctrl_reg\/control_4	A4(0)/pin_input	6.263
iocell35	P15[2]	1	A4(0)	A4(0)/pin_input	A4(0)/pad_out	15.104
Route		1	A4(0)_PAD	A4(0)/pad_out	A4(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_4

A4(0)_PAD:out

21.367

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_4	0.000
Route		1	drive_AB_4	\A_DRIVE_A:Sync:ctrl_reg\/control_4	A4(0)/pin_input	6.263
iocell35	P15[2]	1	A4(0)	A4(0)/pin_input	A4(0)/pad_out	15.104
Route		1	A4(0)_PAD	A4(0)/pad_out	A4(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_5

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_5

nINT0(0)_PAD

74.346

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_5	0.000
Route		1	drive_AB_5	\A_DRIVE_A:Sync:ctrl_reg\/control_5	A5(0)/pin_input	8.299
iocell31	P2[4]	1	A5(0)	A5(0)/pin_input	A5(0)/pad_out	15.349
iocell31	P2[4]	1	A5(0)	A5(0)/pad_out	A5(0)/pad_in	0.000
iocell31	P2[4]	1	A5(0)	A5(0)/pad_in	A5(0)/fb	7.454
Route		1	net_AB_5	A5(0)/fb	Net_499_split/main_5	11.060
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_5	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_5

nINT0(0)_PAD

74.346

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_5	0.000
Route		1	drive_AB_5	\A_DRIVE_A:Sync:ctrl_reg\/control_5	A5(0)/pin_input	8.299
iocell31	P2[4]	1	A5(0)	A5(0)/pin_input	A5(0)/pad_out	15.349
iocell31	P2[4]	1	A5(0)	A5(0)/pad_out	A5(0)/pad_in	0.000
iocell31	P2[4]	1	A5(0)	A5(0)/pad_in	A5(0)/fb	7.454
Route		1	net_AB_5	A5(0)/fb	Net_499_split/main_5	11.060
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_5	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_5

A5(0)_PAD:out

23.648

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_5	0.000
Route		1	drive_AB_5	\A_DRIVE_A:Sync:ctrl_reg\/control_5	A5(0)/pin_input	8.299
iocell31	P2[4]	1	A5(0)	A5(0)/pin_input	A5(0)/pad_out	15.349
Route		1	A5(0)_PAD	A5(0)/pad_out	A5(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_5

A5(0)_PAD:out

23.648

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_5	0.000
Route		1	drive_AB_5	\A_DRIVE_A:Sync:ctrl_reg\/control_5	A5(0)/pin_input	8.299
iocell31	P2[4]	1	A5(0)	A5(0)/pin_input	A5(0)/pad_out	15.349
Route		1	A5(0)_PAD	A5(0)/pad_out	A5(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_6

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_6

nINT0(0)_PAD

70.866

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_6	0.000
Route		1	drive_AB_6	\A_DRIVE_A:Sync:ctrl_reg\/control_6	A6(0)/pin_input	7.487
iocell36	P0[5]	1	A6(0)	A6(0)/pin_input	A6(0)/pad_out	15.023
iocell36	P0[5]	1	A6(0)	A6(0)/pad_out	A6(0)/pad_in	0.000
iocell36	P0[5]	1	A6(0)	A6(0)/pad_in	A6(0)/fb	8.264
Route		1	net_AB_6	A6(0)/fb	Net_499_split/main_10	7.908
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_10	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_6

nINT0(0)_PAD

70.866

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_6	0.000
Route		1	drive_AB_6	\A_DRIVE_A:Sync:ctrl_reg\/control_6	A6(0)/pin_input	7.487
iocell36	P0[5]	1	A6(0)	A6(0)/pin_input	A6(0)/pad_out	15.023
iocell36	P0[5]	1	A6(0)	A6(0)/pad_out	A6(0)/pad_in	0.000
iocell36	P0[5]	1	A6(0)	A6(0)/pad_in	A6(0)/fb	8.264
Route		1	net_AB_6	A6(0)/fb	Net_499_split/main_10	7.908
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_10	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_6

A6(0)_PAD:out

22.510

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_6	0.000
Route		1	drive_AB_6	\A_DRIVE_A:Sync:ctrl_reg\/control_6	A6(0)/pin_input	7.487
iocell36	P0[5]	1	A6(0)	A6(0)/pin_input	A6(0)/pad_out	15.023
Route		1	A6(0)_PAD	A6(0)/pad_out	A6(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_6

A6(0)_PAD:out

22.510

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_6	0.000
Route		1	drive_AB_6	\A_DRIVE_A:Sync:ctrl_reg\/control_6	A6(0)/pin_input	7.487
iocell36	P0[5]	1	A6(0)	A6(0)/pin_input	A6(0)/pad_out	15.023
Route		1	A6(0)_PAD	A6(0)/pad_out	A6(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \A_DRIVE_A:Sync:ctrl_reg\/control_7

Source

Destination

Delay (ns)

\A_DRIVE_A:Sync:ctrl_reg\/control_7

nINT0(0)_PAD

73.136

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_7	0.000
Route		1	drive_AB_7	\A_DRIVE_A:Sync:ctrl_reg\/control_7	A7(0)/pin_input	8.365
iocell32	P2[5]	1	A7(0)	A7(0)/pin_input	A7(0)/pad_out	15.653
iocell32	P2[5]	1	A7(0)	A7(0)/pad_out	A7(0)/pad_in	0.000
iocell32	P2[5]	1	A7(0)	A7(0)/pad_in	A7(0)/fb	7.735
Route		1	net_AB_7	A7(0)/fb	Net_499_split/main_6	9.199
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_6	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_7

nINT0(0)_PAD

73.136

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_7	0.000
Route		1	drive_AB_7	\A_DRIVE_A:Sync:ctrl_reg\/control_7	A7(0)/pin_input	8.365
iocell32	P2[5]	1	A7(0)	A7(0)/pin_input	A7(0)/pad_out	15.653
iocell32	P2[5]	1	A7(0)	A7(0)/pad_out	A7(0)/pad_in	0.000
iocell32	P2[5]	1	A7(0)	A7(0)/pad_in	A7(0)/fb	7.735
Route		1	net_AB_7	A7(0)/fb	Net_499_split/main_6	9.199
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_6	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_7

A7(0)_PAD:out

24.018

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_7	0.000
Route		1	drive_AB_7	\A_DRIVE_A:Sync:ctrl_reg\/control_7	A7(0)/pin_input	8.365
iocell32	P2[5]	1	A7(0)	A7(0)/pin_input	A7(0)/pad_out	15.653
Route		1	A7(0)_PAD	A7(0)/pad_out	A7(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\A_DRIVE_A:Sync:ctrl_reg\/control_7

A7(0)_PAD:out

24.018

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell2	U(3,1)	1	\A_DRIVE_A:Sync:ctrl_reg\	Input Delay	\A_DRIVE_A:Sync:ctrl_reg\/control_7	0.000
Route		1	drive_AB_7	\A_DRIVE_A:Sync:ctrl_reg\/control_7	A7(0)/pin_input	8.365
iocell32	P2[5]	1	A7(0)	A7(0)/pin_input	A7(0)/pad_out	15.653
Route		1	A7(0)_PAD	A7(0)/pad_out	A7(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \CTLREG:Sync:ctrl_reg\/control_0

Source

Destination

Delay (ns)

\CTLREG:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

33.777

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell5	U(2,4)	1	\CTLREG:Sync:ctrl_reg\	Input Delay	\CTLREG:Sync:ctrl_reg\/control_0	0.000
Route		1	tmpOE__bufoe_9_net_0	\CTLREG:Sync:ctrl_reg\/control_0	Net_499/main_0	7.245
macrocell8	U(2,2)	1	Net_499	Net_499/main_0	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\CTLREG:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

33.777

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell5	U(2,4)	1	\CTLREG:Sync:ctrl_reg\	Input Delay	\CTLREG:Sync:ctrl_reg\/control_0	0.000
Route		1	tmpOE__bufoe_9_net_0	\CTLREG:Sync:ctrl_reg\/control_0	Net_499/main_0	7.245
macrocell8	U(2,2)	1	Net_499	Net_499/main_0	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

+ \C_DRIVE:Sync:ctrl_reg\/control_0

Source

Destination

Delay (ns)

\C_DRIVE:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

69.738

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_nIOE	\C_DRIVE:Sync:ctrl_reg\/control_0	nIOE(0)/pin_input	6.823
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pin_input	nIOE(0)/pad_out	15.744
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pad_out	nIOE(0)/pad_in	0.000
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pad_in	nIOE(0)/fb	7.958
Route		1	net_nIOE	nIOE(0)/fb	Net_499_split/main_7	7.029
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_7	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_0

nINT0(0)_PAD

69.738

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_nIOE	\C_DRIVE:Sync:ctrl_reg\/control_0	nIOE(0)/pin_input	6.823
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pin_input	nIOE(0)/pad_out	15.744
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pad_out	nIOE(0)/pad_in	0.000
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pad_in	nIOE(0)/fb	7.958
Route		1	net_nIOE	nIOE(0)/fb	Net_499_split/main_7	7.029
macrocell1	U(3,2)	1	Net_499_split	Net_499_split/main_7	Net_499_split/q	3.350
Route		1	Net_499_split	Net_499_split/q	Net_499/main_1	2.302
macrocell8	U(2,2)	1	Net_499	Net_499/main_1	Net_499/q	3.350
Route		1	Net_499	Net_499/q	nINT0(0)/pin_input	7.801
iocell7	P1[7]	1	nINT0(0)	nINT0(0)/pin_input	nINT0(0)/pad_out	15.381
Route		1	nINT0(0)_PAD	nINT0(0)/pad_out	nINT0(0)_PAD	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_0

nIOE(0)_PAD:out

22.567

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_nIOE	\C_DRIVE:Sync:ctrl_reg\/control_0	nIOE(0)/pin_input	6.823
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pin_input	nIOE(0)/pad_out	15.744
Route		1	nIOE(0)_PAD	nIOE(0)/pad_out	nIOE(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_0

nIOE(0)_PAD:out

22.567

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_0	0.000
Route		1	drive_nIOE	\C_DRIVE:Sync:ctrl_reg\/control_0	nIOE(0)/pin_input	6.823
iocell14	P0[3]	1	nIOE(0)	nIOE(0)/pin_input	nIOE(0)/pad_out	15.744
Route		1	nIOE(0)_PAD	nIOE(0)/pad_out	nIOE(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ \C_DRIVE:Sync:ctrl_reg\/control_2

Source

Destination

Delay (ns)

\C_DRIVE:Sync:ctrl_reg\/control_2

nWR(0)_PAD:out

21.190

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_nWR	\C_DRIVE:Sync:ctrl_reg\/control_2	nWR(0)/pin_input	6.599
iocell15	P3[6]	1	nWR(0)	nWR(0)/pin_input	nWR(0)/pad_out	14.591
Route		1	nWR(0)_PAD	nWR(0)/pad_out	nWR(0)_PAD:out	0.000
Clock					Clock path delay	0.000

\C_DRIVE:Sync:ctrl_reg\/control_2

nWR(0)_PAD:out

21.190

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
controlcell6	U(2,1)	1	\C_DRIVE:Sync:ctrl_reg\	Input Delay	\C_DRIVE:Sync:ctrl_reg\/control_2	0.000
Route		1	drive_nWR	\C_DRIVE:Sync:ctrl_reg\/control_2	nWR(0)/pin_input	6.599
iocell15	P3[6]	1	nWR(0)	nWR(0)/pin_input	nWR(0)/pad_out	14.591
Route		1	nWR(0)_PAD	nWR(0)/pad_out	nWR(0)_PAD:out	0.000
Clock					Clock path delay	0.000

+ phi(0)_PAD

Source

Destination

Delay (ns)

Net_20/q

CLK2MHZ(0)_PAD

41.970

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	Net_20	Net_20/clock_0	Net_20/q	1.250
Route		1	Net_20	Net_20/q	CLK2MHZ(0)/pin_input	7.758
iocell3	P15[6]	1	CLK2MHZ(0)	CLK2MHZ(0)/pin_input	CLK2MHZ(0)/pad_out	19.129
Route		1	CLK2MHZ(0)_PAD	CLK2MHZ(0)/pad_out	CLK2MHZ(0)_PAD	0.000
Clock					Clock path delay	13.833

Project :	URSO180GLUESoC2
Build Time :	08/20/21 22:02:56
Device :	CY8C5888AXI-LP096
Temperature :	-40C - 85/125C
VDDA :	5.00
VDDABUF :	5.00
VDDD :	5.00
VDDIO0 :	5.00
VDDIO1 :	5.00
VDDIO2 :	5.00
VDDIO3 :	5.00
VUSB :	5.00
Voltage :	5.0