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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.677 ns
From           : TEST_BUTTON
To             : WB_UART8_V2:U_MIDIKBD_OB_WB_UART8_V2_1|wb_uart:U_WB_UART|DAT_O_7
From Clock     : --
To Clock       : CLK_BRD
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 31.507 ns
From           : TSK3000A_MCU:U_MIDIKBD_OB_CPU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10
To             : SRAM1_D[11]
From Clock     : CLK_BRD
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 21.678 ns
From           : TEST_BUTTON
To             : SRAM0_A[7]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.156 ns
From           : PS2B_CLK
To             : PS2_W:U_MIDIKBD_OB_PS2_W_1|PS2Controller:U_PS2Controller|ps2ClkIn_q1_Z
From Clock     : --
To Clock       : CLK_REF
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.339 ns
From           : Configurable_LEDS:U_MIDIKBD_OB_LEDS|MIDIKBD__AltSyn_AltiumAlteraDffAsync:INST_LED_B_6|lpm_ff:ff1|dffs[0]
To             : LED_B[6]
From Clock     : CLK_BRD
To Clock       : --
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 13.561 ns
From           : TEST_BUTTON
To             : SRAM1_A[12]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'CLK_BRD'
Slack          : N/A
Required Time  : None
Actual Time    : 18.97 MHz ( period = 52.712 ns )
From           : TSK3000A_MCU:U_MIDIKBD_OB_CPU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10
To             : TSK3000A_MCU:U_MIDIKBD_OB_CPU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41
From Clock     : CLK_BRD
To Clock       : CLK_BRD
Failed Paths   : 0

Type           : Clock Setup: 'ETH_TXC'
Slack          : N/A
Required Time  : None
Actual Time    : 89.29 MHz ( period = 11.200 ns )
From           : EMAC32:U_MIDIKBD_OB_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]
To             : EMAC32:U_MIDIKBD_OB_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15]
From Clock     : ETH_TXC
To Clock       : ETH_TXC
Failed Paths   : 0

Type           : Clock Setup: 'JTAG_NEXUS_TCK'
Slack          : N/A
Required Time  : None
Actual Time    : 121.86 MHz ( period = 8.206 ns )
From           : TSK3000A_OCDS:U_MIDIKBD_OB_CPU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z
To             : TERMINAL:U_MIDIKBD_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]
From Clock     : JTAG_NEXUS_TCK
To Clock       : JTAG_NEXUS_TCK
Failed Paths   : 0

Type           : Clock Setup: 'ETH_RXC'
Slack          : N/A
Required Time  : None
Actual Time    : 122.61 MHz ( period = 8.156 ns )
From           : EMAC32:U_MIDIKBD_OB_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]
To             : EMAC32:U_MIDIKBD_OB_EMAC|MAC32_RX:U_MAC32_RX|rx_error
From Clock     : ETH_RXC
To Clock       : ETH_RXC
Failed Paths   : 0

Type           : Clock Setup: 'CLK_REF'
Slack          : N/A
Required Time  : None
Actual Time    : 164.77 MHz ( period = 6.069 ns )
From           : PS2_W:U_MIDIKBD_OB_PS2_W_1|PS2Controller:U_PS2Controller|genTimeOut_cnt_7__Z
To             : PS2_W:U_MIDIKBD_OB_PS2_W_1|PS2Controller:U_PS2Controller|genTimeOut_cnt_8__Z
From Clock     : CLK_REF
To Clock       : CLK_REF
Failed Paths   : 0

Type           : Clock Hold: 'CLK_BRD'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : WB_ILI9320:U_MIDIKBD_OB_WB_ILI9320_1|ILI9320:U_ILI9320|VideoBufferBase_Reg[9]
To             : WB_ILI9320:U_MIDIKBD_OB_WB_ILI9320_1|ILI9320:U_ILI9320|PixelAddress_Reg_3tmp[9]
From Clock     : CLK_BRD
To Clock       : CLK_BRD
Failed Paths   : 18

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 18

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