Loading plugins phase: Elapsed time ==> 0s.227ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -d CY8C5888AXI-LP096 -s P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 2s.190ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 6s.388ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 URSO180GLUESoC2.v -verilog
======================================================================

======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 URSO180GLUESoC2.v -verilog
======================================================================

======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   vlogfe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 -verilog URSO180GLUESoC2.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Fri Aug 20 22:01:19 2021


======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   vpp
Options  :    -yv2 -q10 URSO180GLUESoC2.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Fri Aug 20 22:01:19 2021

Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\FreqDiv_v1_0\FreqDiv_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cydff_v1_30\cydff_v1_30.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\and_v1_0\and_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nor_v1_0\nor_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nand_v1_0\nand_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyStatusReg_v1_90\CyStatusReg_v1_90.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'

vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'URSO180GLUESoC2.ctl'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\FreqDiv_v1_0\FreqDiv_v1_0.v (line 79, col 40):  Note: Substituting module 'add_vi_vv' for '+'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\FreqDiv_v1_0\FreqDiv_v1_0.v (line 88, col 40):  Note: Substituting module 'add_vi_vv' for '+'.

vlogfe:  No errors.


======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   tovif
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 -verilog URSO180GLUESoC2.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Fri Aug 20 22:01:21 2021

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\codegentemp\URSO180GLUESoC2.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\codegentemp\URSO180GLUESoC2.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\FreqDiv_v1_0\FreqDiv_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cydff_v1_30\cydff_v1_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\and_v1_0\and_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nor_v1_0\nor_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nand_v1_0\nand_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyStatusReg_v1_90\CyStatusReg_v1_90.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.

tovif:  No errors.


======================================================================
Compiling:  URSO180GLUESoC2.v
Program  :   topld
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 -verilog URSO180GLUESoC2.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Fri Aug 20 22:01:21 2021

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\codegentemp\URSO180GLUESoC2.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\codegentemp\URSO180GLUESoC2.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\FreqDiv_v1_0\FreqDiv_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cydff_v1_30\cydff_v1_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\and_v1_0\and_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nor_v1_0\nor_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\nand_v1_0\nand_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyStatusReg_v1_90\CyStatusReg_v1_90.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	\APUclkDivider:MODULE_1:b_31\
	\APUclkDivider:MODULE_1:b_30\
	\APUclkDivider:MODULE_1:b_29\
	\APUclkDivider:MODULE_1:b_28\
	\APUclkDivider:MODULE_1:b_27\
	\APUclkDivider:MODULE_1:b_26\
	\APUclkDivider:MODULE_1:b_25\
	\APUclkDivider:MODULE_1:b_24\
	\APUclkDivider:MODULE_1:b_23\
	\APUclkDivider:MODULE_1:b_22\
	\APUclkDivider:MODULE_1:b_21\
	\APUclkDivider:MODULE_1:b_20\
	\APUclkDivider:MODULE_1:b_19\
	\APUclkDivider:MODULE_1:b_18\
	\APUclkDivider:MODULE_1:b_17\
	\APUclkDivider:MODULE_1:b_16\
	\APUclkDivider:MODULE_1:b_15\
	\APUclkDivider:MODULE_1:b_14\
	\APUclkDivider:MODULE_1:b_13\
	\APUclkDivider:MODULE_1:b_12\
	\APUclkDivider:MODULE_1:b_11\
	\APUclkDivider:MODULE_1:b_10\
	\APUclkDivider:MODULE_1:b_9\
	\APUclkDivider:MODULE_1:b_8\
	\APUclkDivider:MODULE_1:b_7\
	\APUclkDivider:MODULE_1:b_6\
	\APUclkDivider:MODULE_1:b_5\
	\APUclkDivider:MODULE_1:b_4\
	\APUclkDivider:MODULE_1:b_3\
	\APUclkDivider:MODULE_1:b_2\
	\APUclkDivider:MODULE_1:b_1\
	\APUclkDivider:MODULE_1:b_0\
	\APUclkDivider:MODULE_1:g2:a0:a_31\
	\APUclkDivider:MODULE_1:g2:a0:a_30\
	\APUclkDivider:MODULE_1:g2:a0:a_29\
	\APUclkDivider:MODULE_1:g2:a0:a_28\
	\APUclkDivider:MODULE_1:g2:a0:a_27\
	\APUclkDivider:MODULE_1:g2:a0:a_26\
	\APUclkDivider:MODULE_1:g2:a0:a_25\
	\APUclkDivider:MODULE_1:g2:a0:a_24\
	\APUclkDivider:MODULE_1:g2:a0:b_31\
	\APUclkDivider:MODULE_1:g2:a0:b_30\
	\APUclkDivider:MODULE_1:g2:a0:b_29\
	\APUclkDivider:MODULE_1:g2:a0:b_28\
	\APUclkDivider:MODULE_1:g2:a0:b_27\
	\APUclkDivider:MODULE_1:g2:a0:b_26\
	\APUclkDivider:MODULE_1:g2:a0:b_25\
	\APUclkDivider:MODULE_1:g2:a0:b_24\
	\APUclkDivider:MODULE_1:g2:a0:b_23\
	\APUclkDivider:MODULE_1:g2:a0:b_22\
	\APUclkDivider:MODULE_1:g2:a0:b_21\
	\APUclkDivider:MODULE_1:g2:a0:b_20\
	\APUclkDivider:MODULE_1:g2:a0:b_19\
	\APUclkDivider:MODULE_1:g2:a0:b_18\
	\APUclkDivider:MODULE_1:g2:a0:b_17\
	\APUclkDivider:MODULE_1:g2:a0:b_16\
	\APUclkDivider:MODULE_1:g2:a0:b_15\
	\APUclkDivider:MODULE_1:g2:a0:b_14\
	\APUclkDivider:MODULE_1:g2:a0:b_13\
	\APUclkDivider:MODULE_1:g2:a0:b_12\
	\APUclkDivider:MODULE_1:g2:a0:b_11\
	\APUclkDivider:MODULE_1:g2:a0:b_10\
	\APUclkDivider:MODULE_1:g2:a0:b_9\
	\APUclkDivider:MODULE_1:g2:a0:b_8\
	\APUclkDivider:MODULE_1:g2:a0:b_7\
	\APUclkDivider:MODULE_1:g2:a0:b_6\
	\APUclkDivider:MODULE_1:g2:a0:b_5\
	\APUclkDivider:MODULE_1:g2:a0:b_4\
	\APUclkDivider:MODULE_1:g2:a0:b_3\
	\APUclkDivider:MODULE_1:g2:a0:b_2\
	\APUclkDivider:MODULE_1:g2:a0:b_1\
	\APUclkDivider:MODULE_1:g2:a0:b_0\
	\APUclkDivider:MODULE_1:g2:a0:s_31\
	\APUclkDivider:MODULE_1:g2:a0:s_30\
	\APUclkDivider:MODULE_1:g2:a0:s_29\
	\APUclkDivider:MODULE_1:g2:a0:s_28\
	\APUclkDivider:MODULE_1:g2:a0:s_27\
	\APUclkDivider:MODULE_1:g2:a0:s_26\
	\APUclkDivider:MODULE_1:g2:a0:s_25\
	\APUclkDivider:MODULE_1:g2:a0:s_24\
	\APUclkDivider:MODULE_1:g2:a0:s_23\
	\APUclkDivider:MODULE_1:g2:a0:s_22\
	\APUclkDivider:MODULE_1:g2:a0:s_21\
	\APUclkDivider:MODULE_1:g2:a0:s_20\
	\APUclkDivider:MODULE_1:g2:a0:s_19\
	\APUclkDivider:MODULE_1:g2:a0:s_18\
	\APUclkDivider:MODULE_1:g2:a0:s_17\
	\APUclkDivider:MODULE_1:g2:a0:s_16\
	\APUclkDivider:MODULE_1:g2:a0:s_15\
	\APUclkDivider:MODULE_1:g2:a0:s_14\
	\APUclkDivider:MODULE_1:g2:a0:s_13\
	\APUclkDivider:MODULE_1:g2:a0:s_12\
	\APUclkDivider:MODULE_1:g2:a0:s_11\
	\APUclkDivider:MODULE_1:g2:a0:s_10\
	\APUclkDivider:MODULE_1:g2:a0:s_9\
	\APUclkDivider:MODULE_1:g2:a0:s_8\
	\APUclkDivider:MODULE_1:g2:a0:s_7\
	\APUclkDivider:MODULE_1:g2:a0:s_6\
	\APUclkDivider:MODULE_1:g2:a0:s_5\
	\APUclkDivider:MODULE_1:g2:a0:s_4\
	\APUclkDivider:MODULE_1:g2:a0:s_3\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_31\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_30\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_29\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_28\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_27\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_26\
	\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_25\
	\A_DRIVE_C:control_bus_7\
	\A_DRIVE_C:control_bus_6\
	\A_DRIVE_C:control_bus_5\
	\A_DRIVE_C:control_bus_4\
	CREG_7
	\CTLREG:control_out_7\
	CREG_6
	\CTLREG:control_out_6\
	CREG_5
	\CTLREG:control_out_5\
	CREG_4
	\CTLREG:control_out_4\
	CREG_3
	\CTLREG:control_out_3\
	CREG_2
	\CTLREG:control_out_2\
	Net_544
	Net_545
	Net_546
	Net_547

    Synthesized names
	\APUclkDivider:add_vi_vv_MODGEN_1_31\
	\APUclkDivider:add_vi_vv_MODGEN_1_30\
	\APUclkDivider:add_vi_vv_MODGEN_1_29\
	\APUclkDivider:add_vi_vv_MODGEN_1_28\
	\APUclkDivider:add_vi_vv_MODGEN_1_27\
	\APUclkDivider:add_vi_vv_MODGEN_1_26\
	\APUclkDivider:add_vi_vv_MODGEN_1_25\
	\APUclkDivider:add_vi_vv_MODGEN_1_24\
	\APUclkDivider:add_vi_vv_MODGEN_1_23\
	\APUclkDivider:add_vi_vv_MODGEN_1_22\
	\APUclkDivider:add_vi_vv_MODGEN_1_21\
	\APUclkDivider:add_vi_vv_MODGEN_1_20\
	\APUclkDivider:add_vi_vv_MODGEN_1_19\
	\APUclkDivider:add_vi_vv_MODGEN_1_18\
	\APUclkDivider:add_vi_vv_MODGEN_1_17\
	\APUclkDivider:add_vi_vv_MODGEN_1_16\
	\APUclkDivider:add_vi_vv_MODGEN_1_15\
	\APUclkDivider:add_vi_vv_MODGEN_1_14\
	\APUclkDivider:add_vi_vv_MODGEN_1_13\
	\APUclkDivider:add_vi_vv_MODGEN_1_12\
	\APUclkDivider:add_vi_vv_MODGEN_1_11\
	\APUclkDivider:add_vi_vv_MODGEN_1_10\
	\APUclkDivider:add_vi_vv_MODGEN_1_9\
	\APUclkDivider:add_vi_vv_MODGEN_1_8\
	\APUclkDivider:add_vi_vv_MODGEN_1_7\
	\APUclkDivider:add_vi_vv_MODGEN_1_6\
	\APUclkDivider:add_vi_vv_MODGEN_1_5\
	\APUclkDivider:add_vi_vv_MODGEN_1_4\
	\APUclkDivider:add_vi_vv_MODGEN_1_3\

Deleted 128 User equations/components.
Deleted 29 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing one to tmpOE__Button_Pin_net_0
Aliasing tmpOE__LED_Pin_net_0 to tmpOE__Button_Pin_net_0
Aliasing Net_17 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__CLK2MHZ_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__phi_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nRESET_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_5_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__bufoe_4_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__bufoe_3_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__bufoe_2_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__bufoe_1_net_0 to tmpOE__bufoe_6_net_0
Aliasing \TO_MPU_REG:clk\ to zero
Aliasing \TO_MPU_REG:rst\ to zero
Aliasing tmpOE__LIR_net_0 to tmpOE__Button_Pin_net_0
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_23\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_22\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_21\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_20\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_19\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_18\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_17\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_16\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_15\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_14\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_13\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_12\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_11\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_10\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_9\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_8\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_7\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_6\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_5\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_4\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:a_3\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_0\ to tmpOE__Button_Pin_net_0
Aliasing cydff_1S to zero
Aliasing tmpOE__nINT0_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__ST_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nWAIT_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nHALT_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__WDI_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nRD_net_0 to tmpOE__Button_Pin_net_0
Aliasing Net_179 to zero
Aliasing tmpOE__DB1_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nIOE_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nWR_net_0 to tmpOE__Button_Pin_net_0
Aliasing Net_383 to zero
Aliasing tmpOE__DB6_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB4_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB2_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB7_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB5_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB3_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__DB0_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_8_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__bufoe_7_net_0 to tmpOE__bufoe_6_net_0
Aliasing tmpOE__nME_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nRAMCS1_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nRAMCS0_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nROMCS_net_0 to tmpOE__Button_Pin_net_0
Aliasing \D_SENSE:status_7\ to \FROM_MPU_REG:status_7\
Aliasing \D_SENSE:status_6\ to \FROM_MPU_REG:status_6\
Aliasing \D_SENSE:status_5\ to \FROM_MPU_REG:status_5\
Aliasing \D_SENSE:status_4\ to \FROM_MPU_REG:status_4\
Aliasing \D_SENSE:status_3\ to \FROM_MPU_REG:status_3\
Aliasing \D_SENSE:status_2\ to \FROM_MPU_REG:status_2\
Aliasing \D_SENSE:status_1\ to \FROM_MPU_REG:status_1\
Aliasing \D_SENSE:status_0\ to \FROM_MPU_REG:status_0\
Aliasing \A_SENSE_C:status_7\ to zero
Aliasing \A_SENSE_C:status_6\ to zero
Aliasing \A_SENSE_C:status_5\ to zero
Aliasing \A_SENSE_C:status_4\ to zero
Aliasing tmpOE__nBUSREQ_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__nBUSACK_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_10_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_11_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_12_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__A1_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A3_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A5_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A7_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_13_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_14_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_15_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_16_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__A0_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A2_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A4_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A6_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_17_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_18_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_19_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_20_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__A9_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A11_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A13_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A15_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_21_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_22_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_23_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_24_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__A8_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A10_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A12_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A14_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__bufoe_28_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_27_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_26_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_25_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__A16_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A17_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A18_net_0 to tmpOE__Button_Pin_net_0
Aliasing tmpOE__A19_net_0 to tmpOE__Button_Pin_net_0
Aliasing \A_DRIVE_A:clk\ to zero
Aliasing \A_DRIVE_A:rst\ to zero
Aliasing \A_DRIVE_B:clk\ to zero
Aliasing \A_DRIVE_B:rst\ to zero
Aliasing \A_DRIVE_C:clk\ to zero
Aliasing \A_DRIVE_C:rst\ to zero
Aliasing \CTLREG:clk\ to zero
Aliasing \CTLREG:rst\ to zero
Aliasing tmpOE__bufoe_29_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_30_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_31_net_0 to tmpOE__bufoe_9_net_0
Aliasing tmpOE__bufoe_32_net_0 to tmpOE__bufoe_9_net_0
Aliasing \C_DRIVE:clk\ to zero
Aliasing \C_DRIVE:rst\ to zero
Aliasing cydff_1D to \FROM_MPU_REG:status_0\
Removing Lhs of wire one[6] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__LED_Pin_net_0[18] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire Net_17[24] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__CLK2MHZ_net_0[26] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__phi_net_0[33] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nRESET_net_0[41] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire Net_328[46] = \TO_MPU_REG:control_out_3\[81]
Removing Rhs of wire Net_328[46] = \TO_MPU_REG:control_3\[93]
Removing Rhs of wire tmpOE__bufoe_6_net_0[47] = Net_376[50]
Removing Rhs of wire Net_324[52] = \TO_MPU_REG:control_out_1\[79]
Removing Rhs of wire Net_324[52] = \TO_MPU_REG:control_1\[95]
Removing Lhs of wire tmpOE__bufoe_5_net_0[53] = tmpOE__bufoe_6_net_0[47]
Removing Rhs of wire Net_320[57] = \TO_MPU_REG:control_out_6\[85]
Removing Rhs of wire Net_320[57] = \TO_MPU_REG:control_6\[90]
Removing Lhs of wire tmpOE__bufoe_4_net_0[58] = tmpOE__bufoe_6_net_0[47]
Removing Rhs of wire Net_316[62] = \TO_MPU_REG:control_out_4\[82]
Removing Rhs of wire Net_316[62] = \TO_MPU_REG:control_4\[92]
Removing Lhs of wire tmpOE__bufoe_3_net_0[63] = tmpOE__bufoe_6_net_0[47]
Removing Rhs of wire Net_312[67] = \TO_MPU_REG:control_out_2\[80]
Removing Rhs of wire Net_312[67] = \TO_MPU_REG:control_2\[94]
Removing Lhs of wire tmpOE__bufoe_2_net_0[68] = tmpOE__bufoe_6_net_0[47]
Removing Rhs of wire Net_300[72] = \TO_MPU_REG:control_out_0\[78]
Removing Rhs of wire Net_300[72] = \TO_MPU_REG:control_0\[96]
Removing Lhs of wire tmpOE__bufoe_1_net_0[73] = tmpOE__bufoe_6_net_0[47]
Removing Lhs of wire \TO_MPU_REG:clk\[76] = zero[2]
Removing Lhs of wire \TO_MPU_REG:rst\[77] = zero[2]
Removing Rhs of wire Net_332[83] = \TO_MPU_REG:control_out_5\[84]
Removing Rhs of wire Net_332[83] = \TO_MPU_REG:control_5\[91]
Removing Rhs of wire Net_336[86] = \TO_MPU_REG:control_out_7\[87]
Removing Rhs of wire Net_336[86] = \TO_MPU_REG:control_7\[89]
Removing Lhs of wire tmpOE__LIR_net_0[98] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire \APUclkDivider:add_vi_vv_MODGEN_1_2\[107] = \APUclkDivider:MODULE_1:g2:a0:s_2\[267]
Removing Lhs of wire \APUclkDivider:add_vi_vv_MODGEN_1_1\[108] = \APUclkDivider:MODULE_1:g2:a0:s_1\[268]
Removing Lhs of wire \APUclkDivider:add_vi_vv_MODGEN_1_0\[109] = \APUclkDivider:MODULE_1:g2:a0:s_0\[269]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_23\[150] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_22\[151] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_21\[152] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_20\[153] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_19\[154] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_18\[155] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_17\[156] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_16\[157] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_15\[158] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_14\[159] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_13\[160] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_12\[161] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_11\[162] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_10\[163] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_9\[164] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_8\[165] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_7\[166] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_6\[167] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_5\[168] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_4\[169] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_3\[170] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_2\[171] = \APUclkDivider:MODIN1_2\[172]
Removing Lhs of wire \APUclkDivider:MODIN1_2\[172] = \APUclkDivider:count_2\[104]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_1\[173] = \APUclkDivider:MODIN1_1\[174]
Removing Lhs of wire \APUclkDivider:MODIN1_1\[174] = \APUclkDivider:count_1\[105]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:a_0\[175] = \APUclkDivider:MODIN1_0\[176]
Removing Lhs of wire \APUclkDivider:MODIN1_0\[176] = \APUclkDivider:count_0\[106]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_0\[307] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_0\[308] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire cydff_1R[311] = RESET[38]
Removing Lhs of wire cydff_1S[312] = zero[2]
Removing Lhs of wire Net_32[313] = cydff_1[310]
Removing Lhs of wire tmpOE__nINT0_net_0[315] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__ST_net_0[322] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nWAIT_net_0[328] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nHALT_net_0[334] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__WDI_net_0[340] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nRD_net_0[346] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire Net_179[351] = zero[2]
Removing Lhs of wire tmpOE__DB1_net_0[353] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nIOE_net_0[358] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nWR_net_0[364] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire Net_383[381] = zero[2]
Removing Lhs of wire tmpOE__DB6_net_0[383] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB4_net_0[388] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB2_net_0[393] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB7_net_0[398] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB5_net_0[404] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB3_net_0[410] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__DB0_net_0[415] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__bufoe_8_net_0[423] = tmpOE__bufoe_6_net_0[47]
Removing Lhs of wire tmpOE__bufoe_7_net_0[426] = tmpOE__bufoe_6_net_0[47]
Removing Lhs of wire tmpOE__nME_net_0[429] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nRAMCS1_net_0[443] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nRAMCS0_net_0[449] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nROMCS_net_0[455] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire \FROM_MPU_REG:status_7\[460] = net_DB_7[424]
Removing Lhs of wire \FROM_MPU_REG:status_6\[461] = net_DB_6[60]
Removing Lhs of wire \FROM_MPU_REG:status_5\[462] = net_DB_5[427]
Removing Lhs of wire \FROM_MPU_REG:status_4\[463] = net_DB_4[65]
Removing Lhs of wire \FROM_MPU_REG:status_3\[464] = net_DB_3[49]
Removing Lhs of wire \FROM_MPU_REG:status_2\[465] = net_DB_2[70]
Removing Lhs of wire \FROM_MPU_REG:status_1\[466] = net_DB_1[55]
Removing Lhs of wire \FROM_MPU_REG:status_0\[467] = net_DB_0[75]
Removing Lhs of wire \D_SENSE:status_7\[472] = net_DB_7[424]
Removing Lhs of wire \D_SENSE:status_6\[473] = net_DB_6[60]
Removing Lhs of wire \D_SENSE:status_5\[474] = net_DB_5[427]
Removing Lhs of wire \D_SENSE:status_4\[475] = net_DB_4[65]
Removing Lhs of wire \D_SENSE:status_3\[476] = net_DB_3[49]
Removing Lhs of wire \D_SENSE:status_2\[477] = net_DB_2[70]
Removing Lhs of wire \D_SENSE:status_1\[478] = net_DB_1[55]
Removing Lhs of wire \D_SENSE:status_0\[479] = net_DB_0[75]
Removing Lhs of wire \A_SENSE_A:status_7\[481] = net_AB_7[376]
Removing Lhs of wire \A_SENSE_A:status_6\[482] = net_AB_6[483]
Removing Lhs of wire \A_SENSE_A:status_5\[484] = net_AB_5[374]
Removing Lhs of wire \A_SENSE_A:status_4\[485] = net_AB_4[373]
Removing Lhs of wire \A_SENSE_A:status_3\[486] = net_AB_3[372]
Removing Lhs of wire \A_SENSE_A:status_2\[487] = net_AB_2[371]
Removing Lhs of wire \A_SENSE_A:status_1\[488] = net_AB_1[370]
Removing Lhs of wire \A_SENSE_A:status_0\[489] = net_AB_0[380]
Removing Lhs of wire \A_SENSE_B:status_7\[491] = net_AB_15[492]
Removing Lhs of wire \A_SENSE_B:status_6\[493] = net_AB_14[494]
Removing Lhs of wire \A_SENSE_B:status_5\[495] = net_AB_13[496]
Removing Lhs of wire \A_SENSE_B:status_4\[497] = net_AB_12[498]
Removing Lhs of wire \A_SENSE_B:status_3\[499] = net_AB_11[500]
Removing Lhs of wire \A_SENSE_B:status_2\[501] = net_AB_10[502]
Removing Lhs of wire \A_SENSE_B:status_1\[503] = net_AB_9[504]
Removing Lhs of wire \A_SENSE_B:status_0\[505] = net_AB_8[506]
Removing Lhs of wire \A_SENSE_C:status_7\[508] = zero[2]
Removing Lhs of wire \A_SENSE_C:status_6\[509] = zero[2]
Removing Lhs of wire \A_SENSE_C:status_5\[510] = zero[2]
Removing Lhs of wire \A_SENSE_C:status_4\[511] = zero[2]
Removing Lhs of wire \A_SENSE_C:status_3\[512] = net_AB_19[435]
Removing Lhs of wire \A_SENSE_C:status_2\[513] = net_AB_18[514]
Removing Lhs of wire \A_SENSE_C:status_1\[515] = net_AB_17[516]
Removing Lhs of wire \A_SENSE_C:status_0\[517] = net_AB_16[518]
Removing Lhs of wire tmpOE__nBUSREQ_net_0[521] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__nBUSACK_net_0[527] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire drive_AB_1[533] = \A_DRIVE_A:control_out_1\[721]
Removing Rhs of wire drive_AB_1[533] = \A_DRIVE_A:control_1\[730]
Removing Rhs of wire tmpOE__bufoe_9_net_0[534] = CREG_0[536]
Removing Rhs of wire tmpOE__bufoe_9_net_0[534] = \CTLREG:control_out_0\[790]
Removing Rhs of wire tmpOE__bufoe_9_net_0[534] = \CTLREG:control_0\[799]
Removing Rhs of wire drive_AB_3[538] = \A_DRIVE_A:control_out_3\[719]
Removing Rhs of wire drive_AB_3[538] = \A_DRIVE_A:control_3\[728]
Removing Lhs of wire tmpOE__bufoe_10_net_0[539] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_5[542] = \A_DRIVE_A:control_out_5\[717]
Removing Rhs of wire drive_AB_5[542] = \A_DRIVE_A:control_5\[726]
Removing Lhs of wire tmpOE__bufoe_11_net_0[543] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_7[546] = \A_DRIVE_A:control_out_7\[715]
Removing Rhs of wire drive_AB_7[546] = \A_DRIVE_A:control_7\[724]
Removing Lhs of wire tmpOE__bufoe_12_net_0[547] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire tmpOE__A1_net_0[550] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A3_net_0[555] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A5_net_0[560] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A7_net_0[565] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire drive_AB_0[570] = \A_DRIVE_A:control_out_0\[722]
Removing Rhs of wire drive_AB_0[570] = \A_DRIVE_A:control_0\[731]
Removing Lhs of wire tmpOE__bufoe_13_net_0[571] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_2[574] = \A_DRIVE_A:control_out_2\[720]
Removing Rhs of wire drive_AB_2[574] = \A_DRIVE_A:control_2\[729]
Removing Lhs of wire tmpOE__bufoe_14_net_0[575] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_4[578] = \A_DRIVE_A:control_out_4\[718]
Removing Rhs of wire drive_AB_4[578] = \A_DRIVE_A:control_4\[727]
Removing Lhs of wire tmpOE__bufoe_15_net_0[579] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_6[582] = \A_DRIVE_A:control_out_6\[716]
Removing Rhs of wire drive_AB_6[582] = \A_DRIVE_A:control_6\[725]
Removing Lhs of wire tmpOE__bufoe_16_net_0[583] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire tmpOE__A0_net_0[586] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A2_net_0[591] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A4_net_0[596] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A6_net_0[601] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire drive_AB_9[606] = \A_DRIVE_B:control_out_1\[740]
Removing Rhs of wire drive_AB_9[606] = \A_DRIVE_B:control_1\[749]
Removing Lhs of wire tmpOE__bufoe_17_net_0[607] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_11[610] = \A_DRIVE_B:control_out_3\[738]
Removing Rhs of wire drive_AB_11[610] = \A_DRIVE_B:control_3\[747]
Removing Lhs of wire tmpOE__bufoe_18_net_0[611] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_13[614] = \A_DRIVE_B:control_out_5\[736]
Removing Rhs of wire drive_AB_13[614] = \A_DRIVE_B:control_5\[745]
Removing Lhs of wire tmpOE__bufoe_19_net_0[615] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_15[618] = \A_DRIVE_B:control_out_7\[734]
Removing Rhs of wire drive_AB_15[618] = \A_DRIVE_B:control_7\[743]
Removing Lhs of wire tmpOE__bufoe_20_net_0[619] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire tmpOE__A9_net_0[622] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A11_net_0[627] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A13_net_0[632] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A15_net_0[637] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire drive_AB_8[642] = \A_DRIVE_B:control_out_0\[741]
Removing Rhs of wire drive_AB_8[642] = \A_DRIVE_B:control_0\[750]
Removing Lhs of wire tmpOE__bufoe_21_net_0[643] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_10[646] = \A_DRIVE_B:control_out_2\[739]
Removing Rhs of wire drive_AB_10[646] = \A_DRIVE_B:control_2\[748]
Removing Lhs of wire tmpOE__bufoe_22_net_0[647] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_12[650] = \A_DRIVE_B:control_out_4\[737]
Removing Rhs of wire drive_AB_12[650] = \A_DRIVE_B:control_4\[746]
Removing Lhs of wire tmpOE__bufoe_23_net_0[651] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_14[654] = \A_DRIVE_B:control_out_6\[735]
Removing Rhs of wire drive_AB_14[654] = \A_DRIVE_B:control_6\[744]
Removing Lhs of wire tmpOE__bufoe_24_net_0[655] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire tmpOE__A8_net_0[658] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A10_net_0[663] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A12_net_0[668] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A14_net_0[673] = tmpOE__Button_Pin_net_0[1]
Removing Rhs of wire drive_AB_19[678] = \A_DRIVE_C:control_out_3\[761]
Removing Rhs of wire drive_AB_19[678] = \A_DRIVE_C:control_3\[770]
Removing Lhs of wire tmpOE__bufoe_28_net_0[679] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_18[682] = \A_DRIVE_C:control_out_2\[762]
Removing Rhs of wire drive_AB_18[682] = \A_DRIVE_C:control_2\[771]
Removing Lhs of wire tmpOE__bufoe_27_net_0[683] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_17[686] = \A_DRIVE_C:control_out_1\[763]
Removing Rhs of wire drive_AB_17[686] = \A_DRIVE_C:control_1\[772]
Removing Lhs of wire tmpOE__bufoe_26_net_0[687] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_AB_16[690] = \A_DRIVE_C:control_out_0\[764]
Removing Rhs of wire drive_AB_16[690] = \A_DRIVE_C:control_0\[773]
Removing Lhs of wire tmpOE__bufoe_25_net_0[691] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire tmpOE__A16_net_0[694] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A17_net_0[699] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A18_net_0[704] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire tmpOE__A19_net_0[709] = tmpOE__Button_Pin_net_0[1]
Removing Lhs of wire \A_DRIVE_A:clk\[713] = zero[2]
Removing Lhs of wire \A_DRIVE_A:rst\[714] = zero[2]
Removing Lhs of wire \A_DRIVE_B:clk\[732] = zero[2]
Removing Lhs of wire \A_DRIVE_B:rst\[733] = zero[2]
Removing Lhs of wire \A_DRIVE_C:clk\[751] = zero[2]
Removing Lhs of wire \A_DRIVE_C:rst\[752] = zero[2]
Removing Lhs of wire \CTLREG:clk\[774] = zero[2]
Removing Lhs of wire \CTLREG:rst\[775] = zero[2]
Removing Rhs of wire CREG_1[788] = \CTLREG:control_out_1\[789]
Removing Rhs of wire CREG_1[788] = \CTLREG:control_1\[798]
Removing Rhs of wire drive_nME[803] = \C_DRIVE:control_out_1\[817]
Removing Rhs of wire drive_nME[803] = \C_DRIVE:control_1\[835]
Removing Lhs of wire tmpOE__bufoe_29_net_0[804] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_nRD[806] = \C_DRIVE:control_out_3\[819]
Removing Rhs of wire drive_nRD[806] = \C_DRIVE:control_3\[833]
Removing Lhs of wire tmpOE__bufoe_30_net_0[807] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_nIOE[809] = \C_DRIVE:control_out_0\[816]
Removing Rhs of wire drive_nIOE[809] = \C_DRIVE:control_0\[836]
Removing Lhs of wire tmpOE__bufoe_31_net_0[810] = tmpOE__bufoe_9_net_0[534]
Removing Rhs of wire drive_nWR[812] = \C_DRIVE:control_out_2\[818]
Removing Rhs of wire drive_nWR[812] = \C_DRIVE:control_2\[834]
Removing Lhs of wire tmpOE__bufoe_32_net_0[813] = tmpOE__bufoe_9_net_0[534]
Removing Lhs of wire \C_DRIVE:clk\[814] = zero[2]
Removing Lhs of wire \C_DRIVE:rst\[815] = zero[2]
Removing Lhs of wire cydff_1D[842] = net_DB_0[75]

------------------------------------------------------
Aliased 0 equations, 239 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:

Note:  Expanding virtual equation for 'tmpOE__Button_Pin_net_0' (cost = 0):
tmpOE__Button_Pin_net_0 <=  ('1') ;

Note:  Expanding virtual equation for 'zero' (cost = 0):
zero <=  ('0') ;

Note:  Expanding virtual equation for 'RESET' (cost = 0):
RESET <= (not Net_30);

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_1\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_1\ <= (\APUclkDivider:count_0\);

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:s_0\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:s_0\ <= (not \APUclkDivider:count_0\);

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_17\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_17\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_9\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_9\ <=  ('0') ;

Note:  Expanding virtual equation for 'Net_70' (cost = 2):
Net_70 <= ((not net_nIOE and not net_nWR));

Note:  Expanding virtual equation for 'Net_564' (cost = 0):
Net_564 <= (not net_AB_6);

Note:  Expanding virtual equation for 'Net_87' (cost = 0):
Net_87 <= (not net_AB_19);

Note:  Expanding virtual equation for 'Net_89' (cost = 0):
Net_89 <= (not cydff_1);

Note:  Expanding virtual equation for 'Net_554' (cost = 0):
Net_554 <= (not net_nME);

Note:  Expanding virtual equation for 'Net_130' (cost = 0):
Net_130 <= (not net_AB_0);


Substituting virtuals - pass 2:

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_2\' (cost = 4):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_2\ <= ((\APUclkDivider:count_1\ and \APUclkDivider:count_0\));

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:s_1\' (cost = 6):
\APUclkDivider:MODULE_1:g2:a0:s_1\ <= ((not \APUclkDivider:count_0\ and \APUclkDivider:count_1\)
	OR (not \APUclkDivider:count_1\ and \APUclkDivider:count_0\));

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_18\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_18\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_10\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_10\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_3\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_3\ <= ((\APUclkDivider:count_2\ and \APUclkDivider:count_1\ and \APUclkDivider:count_0\));

Note:  Expanding virtual equation for 'ADRAE' (cost = 9):
ADRAE <= ((not net_AB_6 and net_AB_1 and net_AB_2 and net_AB_3 and net_AB_4 and net_AB_5 and net_AB_7));

Note:  Expanding virtual equation for 'Net_348' (cost = 1):
Net_348 <= (not net_AB_1
	OR not net_AB_2
	OR not net_AB_3
	OR not net_AB_4
	OR not net_AB_5
	OR not net_AB_7
	OR net_AB_6);


Substituting virtuals - pass 3:

Note:  Expanding virtual equation for 'Net_505' (cost = 1):
Net_505 <= ((not net_nIOE and not net_AB_0 and not net_nRD and not net_AB_6 and net_AB_1 and net_AB_2 and net_AB_3 and net_AB_4 and net_AB_5 and net_AB_7));

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:s_2\' (cost = 9):
\APUclkDivider:MODULE_1:g2:a0:s_2\ <= ((not \APUclkDivider:count_1\ and \APUclkDivider:count_2\)
	OR (not \APUclkDivider:count_0\ and \APUclkDivider:count_2\)
	OR (not \APUclkDivider:count_2\ and \APUclkDivider:count_1\ and \APUclkDivider:count_0\));

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_19\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_19\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_11\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_11\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_4\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_4\ <=  ('0') ;


Substituting virtuals - pass 4:

Note:  Expanding virtual equation for 'tmpOE__bufoe_6_net_0' (cost = 10):
tmpOE__bufoe_6_net_0 <= (tmpOE__bufoe_9_net_0
	OR (not net_nIOE and not net_AB_0 and not net_nRD and not net_AB_6 and net_AB_1 and net_AB_2 and net_AB_3 and net_AB_4 and net_AB_5 and net_AB_7));

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_20\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_20\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_12\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_12\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_5\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_5\ <=  ('0') ;

Note:  Expanding virtual equation for 'Net_501' (cost = 2):
Net_501 <= ((not net_AB_1 and not tmpOE__bufoe_9_net_0)
	OR (not net_AB_2 and not tmpOE__bufoe_9_net_0)
	OR (not net_AB_3 and not tmpOE__bufoe_9_net_0)
	OR (not net_AB_4 and not tmpOE__bufoe_9_net_0)
	OR (not net_AB_5 and not tmpOE__bufoe_9_net_0)
	OR (not net_AB_7 and not tmpOE__bufoe_9_net_0)
	OR (not tmpOE__bufoe_9_net_0 and net_nIOE)
	OR (not tmpOE__bufoe_9_net_0 and net_AB_0)
	OR (not tmpOE__bufoe_9_net_0 and net_nRD)
	OR (not tmpOE__bufoe_9_net_0 and net_AB_6));


Substituting virtuals - pass 5:

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_21\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_21\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_13\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_13\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_6\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_6\ <=  ('0') ;


Substituting virtuals - pass 6:

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_22\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_22\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_14\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_14\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_7\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_7\ <=  ('0') ;


Substituting virtuals - pass 7:

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_23\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_23\ <=  ('0') ;

Note:  Expanding virtual equation for '\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_15\' (cost = 0):
\APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_15\ <=  ('0') ;


Substituting virtuals - pass 8:

Note: Virtual signal Net_20D Creating a cycle.

Substituting virtuals - pass 9:

Note: Virtual signal \APUclkDivider:not_last_reset\\D\ Creating a cycle.

Substituting virtuals - pass 10:

Note: Virtual signal \APUclkDivider:count_2\\D\ Creating a cycle.

Substituting virtuals - pass 11:

Note: Virtual signal \APUclkDivider:count_1\\D\ Creating a cycle.

Substituting virtuals - pass 12:

Note: Virtual signal \APUclkDivider:count_0\\D\ Creating a cycle.

Substituting virtuals - pass 13:

Note: Virtual signal Net_499 Creating a cycle.

Substituting virtuals - pass 14:

Note:  Expanding virtual equation for 'Net_498' (cost = 1):
Net_498 <= (not CREG_1
	OR not Net_499);


Substituting virtuals - pass 15:


----------------------------------------------------------
Circuit simplification results:

	Expanded 39 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ to zero
Aliasing \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ to zero
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\[278] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\[288] = zero[2]
Removing Lhs of wire \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\[298] = zero[2]
Removing Lhs of wire \APUclkDivider:not_last_reset\\D\[838] = Net_30[39]

------------------------------------------------------
Aliased 0 equations, 4 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Eliminating unused logic - pass 1:


Eliminating unused logic - pass 2:


Substituting virtuals - pass 1:

Note: Virtual signal Net_20D Creating a cycle.

Substituting virtuals - pass 2:

Note: Virtual signal \APUclkDivider:count_2\\D\ Creating a cycle.

Substituting virtuals - pass 3:

Note: Virtual signal \APUclkDivider:count_1\\D\ Creating a cycle.

Substituting virtuals - pass 4:

Note: Virtual signal \APUclkDivider:count_0\\D\ Creating a cycle.

Substituting virtuals - pass 5:

Note: Virtual signal Net_499 Creating a cycle.

Substituting virtuals - pass 6:


----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

topld:  No errors.

CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp
Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -dcpsoc3 URSO180GLUESoC2.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 5s.062ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.4.0.80, Family: PSoC3, Started at: Friday, 20 August 2021 22:01:24
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.cyprj -d CY8C5888AXI-LP096 URSO180GLUESoC2.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.034ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
    Removed wire end \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_24\ kept zero
    Removed wire end \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_16\ kept zero
    Removed wire end \APUclkDivider:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_8\ kept zero
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
</CYPRESSTAG>
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
<CYPRESSTAG name="UDB Routed Clock Assignment">
    Routed Clock: phi(0):iocell.fb
        Effective Clock: phi(0):iocell.fb
        Enable Signal: True
    Routed Clock: Net_135:macrocell.q
        Effective Clock: Net_135:macrocell.q
        Enable Signal: True
</CYPRESSTAG>
ADD: pft.M0040: information: The following 46 pin(s) will be assigned a location by the fitter: A0(0), A1(0), A2(0), A3(0), A4(0), A5(0), A6(0), A7(0), A8(0), A9(0), A10(0), A11(0), A12(0), A13(0), A14(0), A15(0), A16(0), A17(0), A18(0), A19(0), CLK2MHZ(0), DB0(0), DB1(0), DB2(0), DB3(0), DB4(0), DB5(0), DB6(0), DB7(0), LIR(0), nBUSACK(0), nBUSREQ(0), nHALT(0), nINT0(0), nIOE(0), nME(0), nRAMCS0(0), nRAMCS1(0), nRD(0), nRESET(0), nROMCS(0), nWAIT(0), nWR(0), phi(0), ST(0), WDI(0)


Removing unused cells resulting from optimization
Done removing unused cells.
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = Button_Pin(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => Button_Pin(0)__PA ,
            pad => Button_Pin(0)_PAD );
        Properties:
        {
        }

    Pin : Name = LED_Pin(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => LED_Pin(0)__PA ,
            pad => LED_Pin(0)_PAD );
        Properties:
        {
        }

    Pin : Name = CLK2MHZ(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => CLK2MHZ(0)__PA ,
            pin_input => Net_20 ,
            pad => CLK2MHZ(0)_PAD );

    Pin : Name = phi(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => phi(0)__PA ,
            fb => Net_16 ,
            pad => phi(0)_PAD );

    Pin : Name = nRESET(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nRESET(0)__PA ,
            fb => Net_30 ,
            pad => nRESET(0)_PAD );

    Pin : Name = LIR(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => LIR(0)__PA ,
            pad => LIR(0)_PAD );

    Pin : Name = nINT0(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nINT0(0)__PA ,
            pin_input => Net_499 ,
            pad => nINT0(0)_PAD );

    Pin : Name = ST(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => ST(0)__PA ,
            pad => ST(0)_PAD );

    Pin : Name = nWAIT(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nWAIT(0)__PA ,
            pad => nWAIT(0)_PAD );

    Pin : Name = nHALT(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nHALT(0)__PA ,
            pad => nHALT(0)_PAD );

    Pin : Name = WDI(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => WDI(0)__PA ,
            pad => WDI(0)_PAD );

    Pin : Name = nRD(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nRD(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_nRD ,
            pin_input => drive_nRD ,
            pad => nRD(0)_PAD );

    Pin : Name = DB1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB1(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_1 ,
            pin_input => Net_324 ,
            pad => DB1(0)_PAD );

    Pin : Name = nIOE(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nIOE(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_nIOE ,
            pin_input => drive_nIOE ,
            pad => nIOE(0)_PAD );

    Pin : Name = nWR(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nWR(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_nWR ,
            pin_input => drive_nWR ,
            pad => nWR(0)_PAD );

    Pin : Name = DB6(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB6(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_6 ,
            pin_input => Net_320 ,
            pad => DB6(0)_PAD );

    Pin : Name = DB4(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB4(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_4 ,
            pin_input => Net_316 ,
            pad => DB4(0)_PAD );

    Pin : Name = DB2(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB2(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_2 ,
            pin_input => Net_312 ,
            pad => DB2(0)_PAD );

    Pin : Name = DB7(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB7(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_7 ,
            pin_input => Net_336 ,
            pad => DB7(0)_PAD );

    Pin : Name = DB5(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB5(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_5 ,
            pin_input => Net_332 ,
            pad => DB5(0)_PAD );

    Pin : Name = DB3(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB3(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_3 ,
            pin_input => Net_328 ,
            pad => DB3(0)_PAD );

    Pin : Name = DB0(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => DB0(0)__PA ,
            oe => tmpOE__bufoe_6_net_0 ,
            fb => net_DB_0 ,
            pin_input => Net_300 ,
            pad => DB0(0)_PAD );

    Pin : Name = nME(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nME(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_nME ,
            pin_input => drive_nME ,
            pad => nME(0)_PAD );

    Pin : Name = nRAMCS1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nRAMCS1(0)__PA ,
            pin_input => Net_102 ,
            pad => nRAMCS1(0)_PAD );

    Pin : Name = nRAMCS0(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nRAMCS0(0)__PA ,
            pin_input => Net_99 ,
            pad => nRAMCS0(0)_PAD );

    Pin : Name = nROMCS(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nROMCS(0)__PA ,
            pin_input => Net_94 ,
            pad => nROMCS(0)_PAD );

    Pin : Name = nBUSREQ(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nBUSREQ(0)__PA ,
            pad => nBUSREQ(0)_PAD );

    Pin : Name = nBUSACK(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => nBUSACK(0)__PA ,
            pad => nBUSACK(0)_PAD );

    Pin : Name = A1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A1(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_1 ,
            pin_input => drive_AB_1 ,
            pad => A1(0)_PAD );

    Pin : Name = A3(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A3(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_3 ,
            pin_input => drive_AB_3 ,
            pad => A3(0)_PAD );

    Pin : Name = A5(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A5(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_5 ,
            pin_input => drive_AB_5 ,
            pad => A5(0)_PAD );

    Pin : Name = A7(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A7(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_7 ,
            pin_input => drive_AB_7 ,
            pad => A7(0)_PAD );

    Pin : Name = A0(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A0(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_0 ,
            pin_input => drive_AB_0 ,
            pad => A0(0)_PAD );

    Pin : Name = A2(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A2(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_2 ,
            pin_input => drive_AB_2 ,
            pad => A2(0)_PAD );

    Pin : Name = A4(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A4(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_4 ,
            pin_input => drive_AB_4 ,
            pad => A4(0)_PAD );

    Pin : Name = A6(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A6(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_6 ,
            pin_input => drive_AB_6 ,
            pad => A6(0)_PAD );

    Pin : Name = A9(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A9(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_9 ,
            pin_input => drive_AB_9 ,
            pad => A9(0)_PAD );

    Pin : Name = A11(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A11(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_11 ,
            pin_input => drive_AB_11 ,
            pad => A11(0)_PAD );

    Pin : Name = A13(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A13(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_13 ,
            pin_input => drive_AB_13 ,
            pad => A13(0)_PAD );

    Pin : Name = A15(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A15(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_15 ,
            pin_input => drive_AB_15 ,
            pad => A15(0)_PAD );

    Pin : Name = A8(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A8(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_8 ,
            pin_input => drive_AB_8 ,
            pad => A8(0)_PAD );

    Pin : Name = A10(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A10(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_10 ,
            pin_input => drive_AB_10 ,
            pad => A10(0)_PAD );

    Pin : Name = A12(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A12(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_12 ,
            pin_input => drive_AB_12 ,
            pad => A12(0)_PAD );

    Pin : Name = A14(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A14(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_14 ,
            pin_input => drive_AB_14 ,
            pad => A14(0)_PAD );

    Pin : Name = A16(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A16(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_16 ,
            pin_input => drive_AB_16 ,
            pad => A16(0)_PAD );

    Pin : Name = A17(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A17(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_17 ,
            pin_input => drive_AB_17 ,
            pad => A17(0)_PAD );

    Pin : Name = A18(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A18(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_18 ,
            pin_input => drive_AB_18 ,
            pad => A18(0)_PAD );

    Pin : Name = A19(0)
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => A19(0)__PA ,
            oe => tmpOE__bufoe_9_net_0 ,
            fb => net_AB_19 ,
            pin_input => drive_AB_19 ,
            pad => A19(0)_PAD );
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">

    ------------------------------------------------------------
    Macrocell listing
    ------------------------------------------------------------

    MacroCell: Name=Net_499_split, Mode=(Combinatorial)
        Total # of inputs        : 12
        Total # of product terms : 2
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              Net_499 * CREG_1
            + net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_AB_0 * !net_nRD * !net_AB_6
        );
        Output = Net_499_split (fanout=1)

    MacroCell: Name=tmpOE__bufoe_6_net_0, Mode=(Combinatorial)
        Total # of inputs        : 11
        Total # of product terms : 2
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_AB_0 * !net_nRD * !net_AB_6
            + tmpOE__bufoe_9_net_0
        );
        Output = tmpOE__bufoe_6_net_0 (fanout=8)

    MacroCell: Name=Net_135, Mode=(Combinatorial)
        Total # of inputs        : 10
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_nWR * net_AB_0 * !net_AB_6
        );
        Output = Net_135 (fanout=1)

    MacroCell: Name=Net_94, Mode=(Combinatorial)
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !cydff_1 * !net_AB_19 * !net_nME
        );
        Output = Net_94 (fanout=1)

    MacroCell: Name=Net_99, Mode=(Combinatorial)
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              cydff_1 * !net_AB_19 * !net_nME
        );
        Output = Net_99 (fanout=1)

    MacroCell: Name=Net_102, Mode=(Combinatorial)
        Total # of inputs        : 2
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              net_AB_19 * !net_nME
        );
        Output = Net_102 (fanout=1)

    MacroCell: Name=Net_259, Mode=(Combinatorial)
        Total # of inputs        : 10
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_nWR * !net_AB_0 * !net_AB_6
        );
        Output = Net_259 (fanout=1)

    MacroCell: Name=Net_499, Mode=(Combinatorial)
        Total # of inputs        : 2
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !tmpOE__bufoe_9_net_0 * !Net_499_split
        );
        Output = Net_499 (fanout=2)

    MacroCell: Name=Net_20, Mode=(D-Register)
        Total # of inputs        : 6
        Total # of product terms : 4
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              Net_20 * Net_30 * !\APUclkDivider:count_1\
            + Net_20 * Net_30 * !\APUclkDivider:count_0\
            + Net_30 * !\APUclkDivider:not_last_reset\
            + Net_30 * \APUclkDivider:count_2\ * \APUclkDivider:count_1\ * 
              \APUclkDivider:count_0\
        );
        Output = Net_20 (fanout=2)

    MacroCell: Name=\APUclkDivider:not_last_reset\, Mode=(D-Register)
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              Net_30
        );
        Output = \APUclkDivider:not_last_reset\ (fanout=4)

    MacroCell: Name=\APUclkDivider:count_2\, Mode=(T-Register)
        Total # of inputs        : 5
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !Net_30 * \APUclkDivider:count_2\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_1\ * \APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_2\ (fanout=2)

    MacroCell: Name=\APUclkDivider:count_1\, Mode=(T-Register)
        Total # of inputs        : 4
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !Net_30 * \APUclkDivider:count_1\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_1\ (fanout=3)

    MacroCell: Name=\APUclkDivider:count_0\, Mode=(D-Register)
        Total # of inputs        : 3
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              Net_30 * !\APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_0\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              !\APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_0\ (fanout=4)

    MacroCell: Name=cydff_1, Mode=(D-Register)
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (Net_135)
            Reset  = !(Net_30)
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_DB_0
        );
        Output = cydff_1 (fanout=2)
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">

    ------------------------------------------------------------
    Status register listing
    ------------------------------------------------------------

    statuscell: Name =\FROM_MPU_REG:sts:sts_reg\
        PORT MAP (
            status_7 => net_DB_7 ,
            status_6 => net_DB_6 ,
            status_5 => net_DB_5 ,
            status_4 => net_DB_4 ,
            status_3 => net_DB_3 ,
            status_2 => net_DB_2 ,
            status_1 => net_DB_1 ,
            status_0 => net_DB_0 );
        Properties:
        {
            cy_force_order = 1
            cy_md_select = "00000000"
        }
        Clock Enable: True

    statuscell: Name =\D_SENSE:sts:sts_reg\
        PORT MAP (
            status_7 => net_DB_7 ,
            status_6 => net_DB_6 ,
            status_5 => net_DB_5 ,
            status_4 => net_DB_4 ,
            status_3 => net_DB_3 ,
            status_2 => net_DB_2 ,
            status_1 => net_DB_1 ,
            status_0 => net_DB_0 );
        Properties:
        {
            cy_force_order = 1
            cy_md_select = "00000000"
        }
        Clock Enable: True

    statuscell: Name =\A_SENSE_A:sts:sts_reg\
        PORT MAP (
            status_7 => net_AB_7 ,
            status_6 => net_AB_6 ,
            status_5 => net_AB_5 ,
            status_4 => net_AB_4 ,
            status_3 => net_AB_3 ,
            status_2 => net_AB_2 ,
            status_1 => net_AB_1 ,
            status_0 => net_AB_0 );
        Properties:
        {
            cy_force_order = 1
            cy_md_select = "00000000"
        }
        Clock Enable: True

    statuscell: Name =\A_SENSE_B:sts:sts_reg\
        PORT MAP (
            status_7 => net_AB_15 ,
            status_6 => net_AB_14 ,
            status_5 => net_AB_13 ,
            status_4 => net_AB_12 ,
            status_3 => net_AB_11 ,
            status_2 => net_AB_10 ,
            status_1 => net_AB_9 ,
            status_0 => net_AB_8 );
        Properties:
        {
            cy_force_order = 1
            cy_md_select = "00000000"
        }
        Clock Enable: True

    statuscell: Name =\A_SENSE_C:sts:sts_reg\
        PORT MAP (
            status_3 => net_AB_19 ,
            status_2 => net_AB_18 ,
            status_1 => net_AB_17 ,
            status_0 => net_AB_16 );
        Properties:
        {
            cy_force_order = 1
            cy_md_select = "00000000"
        }
        Clock Enable: True
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">

    ------------------------------------------------------------
    Control register listing
    ------------------------------------------------------------

    controlcell: Name =\TO_MPU_REG:Sync:ctrl_reg\
        PORT MAP (
            control_7 => Net_336 ,
            control_6 => Net_320 ,
            control_5 => Net_332 ,
            control_4 => Net_316 ,
            control_3 => Net_328 ,
            control_2 => Net_312 ,
            control_1 => Net_324 ,
            control_0 => Net_300 );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True

    controlcell: Name =\A_DRIVE_A:Sync:ctrl_reg\
        PORT MAP (
            control_7 => drive_AB_7 ,
            control_6 => drive_AB_6 ,
            control_5 => drive_AB_5 ,
            control_4 => drive_AB_4 ,
            control_3 => drive_AB_3 ,
            control_2 => drive_AB_2 ,
            control_1 => drive_AB_1 ,
            control_0 => drive_AB_0 );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True

    controlcell: Name =\A_DRIVE_B:Sync:ctrl_reg\
        PORT MAP (
            control_7 => drive_AB_15 ,
            control_6 => drive_AB_14 ,
            control_5 => drive_AB_13 ,
            control_4 => drive_AB_12 ,
            control_3 => drive_AB_11 ,
            control_2 => drive_AB_10 ,
            control_1 => drive_AB_9 ,
            control_0 => drive_AB_8 );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True

    controlcell: Name =\A_DRIVE_C:Sync:ctrl_reg\
        PORT MAP (
            control_7 => \A_DRIVE_C:control_7\ ,
            control_6 => \A_DRIVE_C:control_6\ ,
            control_5 => \A_DRIVE_C:control_5\ ,
            control_4 => \A_DRIVE_C:control_4\ ,
            control_3 => drive_AB_19 ,
            control_2 => drive_AB_18 ,
            control_1 => drive_AB_17 ,
            control_0 => drive_AB_16 );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True

    controlcell: Name =\CTLREG:Sync:ctrl_reg\
        PORT MAP (
            control_7 => \CTLREG:control_7\ ,
            control_6 => \CTLREG:control_6\ ,
            control_5 => \CTLREG:control_5\ ,
            control_4 => \CTLREG:control_4\ ,
            control_3 => \CTLREG:control_3\ ,
            control_2 => \CTLREG:control_2\ ,
            control_1 => CREG_1 ,
            control_0 => tmpOE__bufoe_9_net_0 );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True

    controlcell: Name =\C_DRIVE:Sync:ctrl_reg\
        PORT MAP (
            control_7 => \C_DRIVE:control_7\ ,
            control_6 => \C_DRIVE:control_6\ ,
            control_5 => \C_DRIVE:control_5\ ,
            control_4 => \C_DRIVE:control_4\ ,
            control_3 => drive_nRD ,
            control_2 => drive_nWR ,
            control_1 => drive_nME ,
            control_0 => drive_nIOE );
        Properties:
        {
            cy_ctrl_mode_0 = "00000000"
            cy_ctrl_mode_1 = "00000000"
            cy_ext_reset = 0
            cy_force_order = 1
            cy_init_value = "00000000"
        }
        Clock Enable: True
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">

    ------------------------------------------------------------
    Interrupt listing
    ------------------------------------------------------------

    interrupt: Name =rxint
        PORT MAP (
            interrupt => Net_259 );
        Properties:
        {
            int_type = "00"
            is_nmi = 0
        }
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital Clocks                :    0 :    8 :    8 :  0.00 %
Analog Clocks                 :    0 :    4 :    4 :  0.00 %
CapSense Buffers              :    0 :    2 :    2 :  0.00 %
Digital Filter Block          :    0 :    1 :    1 :  0.00 %
Interrupts                    :    1 :   31 :   32 :  3.13 %
IO                            :   51 :   21 :   72 : 70.83 %
Segment LCD                   :    0 :    1 :    1 :  0.00 %
CAN 2.0b                      :    0 :    1 :    1 :  0.00 %
I2C                           :    0 :    1 :    1 :  0.00 %
USB                           :    0 :    1 :    1 :  0.00 %
DMA Channels                  :    0 :   24 :   24 :  0.00 %
Timer                         :    0 :    4 :    4 :  0.00 %
UDB                           :      :      :      :        
  Macrocells                  :   14 :  178 :  192 :  7.29 %
  Unique P-terms              :   21 :  363 :  384 :  5.47 %
  Total P-terms               :   22 :      :      :        
  Datapath Cells              :    0 :   24 :   24 :  0.00 %
  Status Cells                :    5 :   19 :   24 : 20.83 %
    Status Registers          :    5 :      :      :        
  Control Cells               :    6 :   18 :   24 : 25.00 %
    Control Registers         :    6 :      :      :        
Opamp                         :    0 :    4 :    4 :  0.00 %
Comparator                    :    0 :    4 :    4 :  0.00 %
Delta-Sigma ADC               :    0 :    1 :    1 :  0.00 %
LPF                           :    0 :    2 :    2 :  0.00 %
SAR ADC                       :    0 :    2 :    2 :  0.00 %
Analog (SC/CT) Blocks         :    0 :    4 :    4 :  0.00 %
DAC                           :      :      :      :        
  VIDAC                       :    0 :    4 :    4 :  0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 13s.263ms
Tech Mapping phase: Elapsed time ==> 13s.387ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
Initial Analog Placement Results:
IO_2@[IOP=(1)][IoId=(2)] : Button_Pin(0) (fixed)
IO_7@[IOP=(6)][IoId=(7)] : LED_Pin(0) (fixed)
Analog Placement phase: Elapsed time ==> 0s.075ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.019ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 0s.351ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
Warning: sta.M0019: URSO180GLUESoC2.rpt: Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at Net_499_split/main_0 --> Net_499_split/q  (File=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.rpt)
<CYPRESSTAG name="Detailed placement messages">
Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at Net_499_split/main_0 --> Net_499_split/q 
I2076: Total run-time: 2.5 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary" expanded>

------------------------------------------------------------
PLD Packing Summary
------------------------------------------------------------
            Resource Type : Used : Free :  Max :  % Used
    ====================================================
                     PLDs :   11 :   37 :   48 :  22.92%

<CYPRESSTAG name="PLD Statistics">

        PLD Resource Type :     Average/LAB
    =======================================
                   Inputs :            5.82
                   Pterms :            2.00
               Macrocells :            1.27
</CYPRESSTAG>
<CYPRESSTAG name="Packed PLD Contents">
Packed PLD Contents not displayed at this verbose level.</CYPRESSTAG>
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.060ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.115ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          8 :       6.38 :       1.75
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
UDB [UDB=(0,0)] is empty.
UDB [UDB=(0,1)] is empty.
UDB [UDB=(0,2)] is empty.
UDB [UDB=(0,3)] is empty.
UDB [UDB=(0,4)] is empty.
UDB [UDB=(0,5)] is empty.
UDB [UDB=(1,0)] is empty.
UDB [UDB=(1,1)] is empty.
UDB [UDB=(1,2)] is empty.
UDB [UDB=(1,3)] is empty.
UDB [UDB=(1,4)] is empty.
UDB [UDB=(1,5)] is empty.
UDB [UDB=(2,0)] is empty.
UDB [UDB=(2,1)] contents:
statuscell: Name =\A_SENSE_C:sts:sts_reg\
    PORT MAP (
        status_3 => net_AB_19 ,
        status_2 => net_AB_18 ,
        status_1 => net_AB_17 ,
        status_0 => net_AB_16 );
    Properties:
    {
        cy_force_order = 1
        cy_md_select = "00000000"
    }
    Clock Enable: True

controlcell: Name =\C_DRIVE:Sync:ctrl_reg\
    PORT MAP (
        control_7 => \C_DRIVE:control_7\ ,
        control_6 => \C_DRIVE:control_6\ ,
        control_5 => \C_DRIVE:control_5\ ,
        control_4 => \C_DRIVE:control_4\ ,
        control_3 => drive_nRD ,
        control_2 => drive_nWR ,
        control_1 => drive_nME ,
        control_0 => drive_nIOE );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(2,2)] contents:
LAB@[UDB=(2,2)][LB=0] #macrocells=1, #inputs=2, #pterms=1
{
    [McSlotId=0]: (empty)
    [McSlotId=1]:     MacroCell: Name=Net_499, Mode=(Combinatorial) @ [UDB=(2,2)][LB=0][MC=1]
        Total # of inputs        : 2
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !tmpOE__bufoe_9_net_0 * !Net_499_split
        );
        Output = Net_499 (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

UDB [UDB=(2,3)] contents:
LAB@[UDB=(2,3)][LB=1] #macrocells=1, #inputs=3, #pterms=1
{
    [McSlotId=0]: (empty)
    [McSlotId=1]:     MacroCell: Name=Net_99, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=1]
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              cydff_1 * !net_AB_19 * !net_nME
        );
        Output = Net_99 (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

UDB [UDB=(2,4)] contents:
LAB@[UDB=(2,4)][LB=0] #macrocells=1, #inputs=3, #pterms=2
{
    [McSlotId=0]: (empty)
    [McSlotId=1]: (empty)
    [McSlotId=2]:     MacroCell: Name=\APUclkDivider:count_0\, Mode=(D-Register) @ [UDB=(2,4)][LB=0][MC=2]
        Total # of inputs        : 3
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              Net_30 * !\APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_0\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              !\APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_0\ (fanout=4)
        Properties               : 
        {
        }

    [McSlotId=3]: (empty)
}

LAB@[UDB=(2,4)][LB=1] #macrocells=3, #inputs=6, #pterms=8
{
    [McSlotId=0]:     MacroCell: Name=Net_20, Mode=(D-Register) @ [UDB=(2,4)][LB=1][MC=0]
        Total # of inputs        : 6
        Total # of product terms : 4
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              Net_20 * Net_30 * !\APUclkDivider:count_1\
            + Net_20 * Net_30 * !\APUclkDivider:count_0\
            + Net_30 * !\APUclkDivider:not_last_reset\
            + Net_30 * \APUclkDivider:count_2\ * \APUclkDivider:count_1\ * 
              \APUclkDivider:count_0\
        );
        Output = Net_20 (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=\APUclkDivider:count_2\, Mode=(T-Register) @ [UDB=(2,4)][LB=1][MC=1]
        Total # of inputs        : 5
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !Net_30 * \APUclkDivider:count_2\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_1\ * \APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_2\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=2]:     MacroCell: Name=\APUclkDivider:count_1\, Mode=(T-Register) @ [UDB=(2,4)][LB=1][MC=2]
        Total # of inputs        : 4
        Total # of product terms : 2
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !Net_30 * \APUclkDivider:count_1\
            + Net_30 * \APUclkDivider:not_last_reset\ * 
              \APUclkDivider:count_0\
        );
        Output = \APUclkDivider:count_1\ (fanout=3)
        Properties               : 
        {
        }

    [McSlotId=3]: (empty)
}

controlcell: Name =\CTLREG:Sync:ctrl_reg\
    PORT MAP (
        control_7 => \CTLREG:control_7\ ,
        control_6 => \CTLREG:control_6\ ,
        control_5 => \CTLREG:control_5\ ,
        control_4 => \CTLREG:control_4\ ,
        control_3 => \CTLREG:control_3\ ,
        control_2 => \CTLREG:control_2\ ,
        control_1 => CREG_1 ,
        control_0 => tmpOE__bufoe_9_net_0 );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(2,5)] is empty.
UDB [UDB=(3,0)] is empty.
UDB [UDB=(3,1)] contents:
LAB@[UDB=(3,1)][LB=0] #macrocells=1, #inputs=10, #pterms=1
{
    [McSlotId=0]:     MacroCell: Name=Net_259, Mode=(Combinatorial) @ [UDB=(3,1)][LB=0][MC=0]
        Total # of inputs        : 10
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_nWR * !net_AB_0 * !net_AB_6
        );
        Output = Net_259 (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

LAB@[UDB=(3,1)][LB=1] #macrocells=1, #inputs=3, #pterms=1
{
    [McSlotId=0]: (empty)
    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]:     MacroCell: Name=Net_94, Mode=(Combinatorial) @ [UDB=(3,1)][LB=1][MC=3]
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !cydff_1 * !net_AB_19 * !net_nME
        );
        Output = Net_94 (fanout=1)
        Properties               : 
        {
        }
}

statuscell: Name =\A_SENSE_A:sts:sts_reg\
    PORT MAP (
        status_7 => net_AB_7 ,
        status_6 => net_AB_6 ,
        status_5 => net_AB_5 ,
        status_4 => net_AB_4 ,
        status_3 => net_AB_3 ,
        status_2 => net_AB_2 ,
        status_1 => net_AB_1 ,
        status_0 => net_AB_0 );
    Properties:
    {
        cy_force_order = 1
        cy_md_select = "00000000"
    }
    Clock Enable: True

controlcell: Name =\A_DRIVE_A:Sync:ctrl_reg\
    PORT MAP (
        control_7 => drive_AB_7 ,
        control_6 => drive_AB_6 ,
        control_5 => drive_AB_5 ,
        control_4 => drive_AB_4 ,
        control_3 => drive_AB_3 ,
        control_2 => drive_AB_2 ,
        control_1 => drive_AB_1 ,
        control_0 => drive_AB_0 );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(3,2)] contents:
LAB@[UDB=(3,2)][LB=0] #macrocells=1, #inputs=11, #pterms=2
{
    [McSlotId=0]:     MacroCell: Name=tmpOE__bufoe_6_net_0, Mode=(Combinatorial) @ [UDB=(3,2)][LB=0][MC=0]
        Total # of inputs        : 11
        Total # of product terms : 2
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_AB_0 * !net_nRD * !net_AB_6
            + tmpOE__bufoe_9_net_0
        );
        Output = tmpOE__bufoe_6_net_0 (fanout=8)
        Properties               : 
        {
        }

    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

LAB@[UDB=(3,2)][LB=1] #macrocells=1, #inputs=12, #pterms=2
{
    [McSlotId=0]: (empty)
    [McSlotId=1]: (empty)
    [McSlotId=2]:     MacroCell: Name=Net_499_split, Mode=(Combinatorial) @ [UDB=(3,2)][LB=1][MC=2]
        Total # of inputs        : 12
        Total # of product terms : 2
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              Net_499 * CREG_1
            + net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_AB_0 * !net_nRD * !net_AB_6
        );
        Output = Net_499_split (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=3]: (empty)
}

statuscell: Name =\D_SENSE:sts:sts_reg\
    PORT MAP (
        status_7 => net_DB_7 ,
        status_6 => net_DB_6 ,
        status_5 => net_DB_5 ,
        status_4 => net_DB_4 ,
        status_3 => net_DB_3 ,
        status_2 => net_DB_2 ,
        status_1 => net_DB_1 ,
        status_0 => net_DB_0 );
    Properties:
    {
        cy_force_order = 1
        cy_md_select = "00000000"
    }
    Clock Enable: True

controlcell: Name =\A_DRIVE_C:Sync:ctrl_reg\
    PORT MAP (
        control_7 => \A_DRIVE_C:control_7\ ,
        control_6 => \A_DRIVE_C:control_6\ ,
        control_5 => \A_DRIVE_C:control_5\ ,
        control_4 => \A_DRIVE_C:control_4\ ,
        control_3 => drive_AB_19 ,
        control_2 => drive_AB_18 ,
        control_1 => drive_AB_17 ,
        control_0 => drive_AB_16 );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(3,3)] contents:
LAB@[UDB=(3,3)][LB=0] #macrocells=2, #inputs=11, #pterms=2
{
    [McSlotId=0]:     MacroCell: Name=Net_135, Mode=(Combinatorial) @ [UDB=(3,3)][LB=0][MC=0]
        Total # of inputs        : 10
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_AB_1 * net_AB_2 * net_AB_3 * net_AB_4 * net_AB_5 * net_AB_7 * 
              !net_nIOE * !net_nWR * net_AB_0 * !net_AB_6
        );
        Output = Net_135 (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=cydff_1, Mode=(D-Register) @ [UDB=(3,3)][LB=0][MC=1]
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (Net_135)
            Reset  = !(Net_30)
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              net_DB_0
        );
        Output = cydff_1 (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

LAB@[UDB=(3,3)][LB=1] #macrocells=1, #inputs=2, #pterms=1
{
    [McSlotId=0]:     MacroCell: Name=Net_102, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=0]
        Total # of inputs        : 2
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              net_AB_19 * !net_nME
        );
        Output = Net_102 (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

statuscell: Name =\FROM_MPU_REG:sts:sts_reg\
    PORT MAP (
        status_7 => net_DB_7 ,
        status_6 => net_DB_6 ,
        status_5 => net_DB_5 ,
        status_4 => net_DB_4 ,
        status_3 => net_DB_3 ,
        status_2 => net_DB_2 ,
        status_1 => net_DB_1 ,
        status_0 => net_DB_0 );
    Properties:
    {
        cy_force_order = 1
        cy_md_select = "00000000"
    }
    Clock Enable: True

controlcell: Name =\TO_MPU_REG:Sync:ctrl_reg\
    PORT MAP (
        control_7 => Net_336 ,
        control_6 => Net_320 ,
        control_5 => Net_332 ,
        control_4 => Net_316 ,
        control_3 => Net_328 ,
        control_2 => Net_312 ,
        control_1 => Net_324 ,
        control_0 => Net_300 );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(3,4)] contents:
LAB@[UDB=(3,4)][LB=1] #macrocells=1, #inputs=1, #pterms=1
{
    [McSlotId=0]: (empty)
    [McSlotId=1]:     MacroCell: Name=\APUclkDivider:not_last_reset\, Mode=(D-Register) @ [UDB=(3,4)][LB=1][MC=1]
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (Net_16)
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              Net_30
        );
        Output = \APUclkDivider:not_last_reset\ (fanout=4)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

statuscell: Name =\A_SENSE_B:sts:sts_reg\
    PORT MAP (
        status_7 => net_AB_15 ,
        status_6 => net_AB_14 ,
        status_5 => net_AB_13 ,
        status_4 => net_AB_12 ,
        status_3 => net_AB_11 ,
        status_2 => net_AB_10 ,
        status_1 => net_AB_9 ,
        status_0 => net_AB_8 );
    Properties:
    {
        cy_force_order = 1
        cy_md_select = "00000000"
    }
    Clock Enable: True

controlcell: Name =\A_DRIVE_B:Sync:ctrl_reg\
    PORT MAP (
        control_7 => drive_AB_15 ,
        control_6 => drive_AB_14 ,
        control_5 => drive_AB_13 ,
        control_4 => drive_AB_12 ,
        control_3 => drive_AB_11 ,
        control_2 => drive_AB_10 ,
        control_1 => drive_AB_9 ,
        control_0 => drive_AB_8 );
    Properties:
    {
        cy_ctrl_mode_0 = "00000000"
        cy_ctrl_mode_1 = "00000000"
        cy_ext_reset = 0
        cy_force_order = 1
        cy_init_value = "00000000"
    }
    Clock Enable: True

UDB [UDB=(3,5)] is empty.
Intr container @ [IntrContainer=(0)]: 
  Intr@ [IntrContainer=(0)][IntrId=(0)] 
    interrupt: Name =rxint
        PORT MAP (
            interrupt => Net_259 );
        Properties:
        {
            int_type = "00"
            is_nmi = 0
        }
Drq container @ [DrqContainer=(0)]: empty
Port 0 contains the following IO cells:
[IoId=0]: 
Pin : Name = A11(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A11(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_11 ,
        pin_input => drive_AB_11 ,
        pad => A11(0)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = A8(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A8(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_8 ,
        pin_input => drive_AB_8 ,
        pad => A8(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = DB3(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB3(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_3 ,
        pin_input => Net_328 ,
        pad => DB3(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = nIOE(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nIOE(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_nIOE ,
        pin_input => drive_nIOE ,
        pad => nIOE(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = A14(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A14(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_14 ,
        pin_input => drive_AB_14 ,
        pad => A14(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = A6(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A6(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_6 ,
        pin_input => drive_AB_6 ,
        pad => A6(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = DB2(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB2(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_2 ,
        pin_input => Net_312 ,
        pad => DB2(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = A15(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A15(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_15 ,
        pin_input => drive_AB_15 ,
        pad => A15(0)_PAD );
    Properties:
    {
    }

Port 1 contains the following IO cells:
[IoId=2]: 
Pin : Name = Button_Pin(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => Button_Pin(0)__PA ,
        pad => Button_Pin(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = LIR(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => LIR(0)__PA ,
        pad => LIR(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = nWAIT(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nWAIT(0)__PA ,
        pad => nWAIT(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = ST(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => ST(0)__PA ,
        pad => ST(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = nINT0(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nINT0(0)__PA ,
        pin_input => Net_499 ,
        pad => nINT0(0)_PAD );
    Properties:
    {
    }

Port 2 contains the following IO cells:
[IoId=1]: 
Pin : Name = A17(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A17(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_17 ,
        pin_input => drive_AB_17 ,
        pad => A17(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = nRAMCS0(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nRAMCS0(0)__PA ,
        pin_input => Net_99 ,
        pad => nRAMCS0(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = nRESET(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nRESET(0)__PA ,
        fb => Net_30 ,
        pad => nRESET(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = A5(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A5(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_5 ,
        pin_input => drive_AB_5 ,
        pad => A5(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = A7(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A7(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_7 ,
        pin_input => drive_AB_7 ,
        pad => A7(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = phi(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => phi(0)__PA ,
        fb => Net_16 ,
        pad => phi(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = nBUSACK(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nBUSACK(0)__PA ,
        pad => nBUSACK(0)_PAD );
    Properties:
    {
    }

Port 3 contains the following IO cells:
[IoId=1]: 
Pin : Name = nRAMCS1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nRAMCS1(0)__PA ,
        pin_input => Net_102 ,
        pad => nRAMCS1(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = DB5(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB5(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_5 ,
        pin_input => Net_332 ,
        pad => DB5(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = A18(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A18(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_18 ,
        pin_input => drive_AB_18 ,
        pad => A18(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = A2(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A2(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_2 ,
        pin_input => drive_AB_2 ,
        pad => A2(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = nRD(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nRD(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_nRD ,
        pin_input => drive_nRD ,
        pad => nRD(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = nWR(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nWR(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_nWR ,
        pin_input => drive_nWR ,
        pad => nWR(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = nHALT(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nHALT(0)__PA ,
        pad => nHALT(0)_PAD );
    Properties:
    {
    }

Port 4 contains the following IO cells:
[IoId=0]: 
Pin : Name = DB7(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB7(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_7 ,
        pin_input => Net_336 ,
        pad => DB7(0)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = A10(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A10(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_10 ,
        pin_input => drive_AB_10 ,
        pad => A10(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = A13(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A13(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_13 ,
        pin_input => drive_AB_13 ,
        pad => A13(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = A12(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A12(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_12 ,
        pin_input => drive_AB_12 ,
        pad => A12(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = DB6(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB6(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_6 ,
        pin_input => Net_320 ,
        pad => DB6(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = A16(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A16(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_16 ,
        pin_input => drive_AB_16 ,
        pad => A16(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = DB4(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB4(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_4 ,
        pin_input => Net_316 ,
        pad => DB4(0)_PAD );
    Properties:
    {
    }

Port 5 contains the following IO cells:
[IoId=2]: 
Pin : Name = nME(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nME(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_nME ,
        pin_input => drive_nME ,
        pad => nME(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = nBUSREQ(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nBUSREQ(0)__PA ,
        pad => nBUSREQ(0)_PAD );
    Properties:
    {
    }

Port 6 contains the following IO cells:
[IoId=0]: 
Pin : Name = A0(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A0(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_0 ,
        pin_input => drive_AB_0 ,
        pad => A0(0)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = DB1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB1(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_1 ,
        pin_input => Net_324 ,
        pad => DB1(0)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = LED_Pin(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => LED_Pin(0)__PA ,
        pad => LED_Pin(0)_PAD );
    Properties:
    {
    }

Port 12 contains the following IO cells:
[IoId=2]: 
Pin : Name = A1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A1(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_1 ,
        pin_input => drive_AB_1 ,
        pad => A1(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = A9(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A9(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_9 ,
        pin_input => drive_AB_9 ,
        pad => A9(0)_PAD );
    Properties:
    {
    }

Port 15 contains the following IO cells:
[IoId=0]: 
Pin : Name = A3(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A3(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_3 ,
        pin_input => drive_AB_3 ,
        pad => A3(0)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = nROMCS(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => nROMCS(0)__PA ,
        pin_input => Net_94 ,
        pad => nROMCS(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = A4(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A4(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_4 ,
        pin_input => drive_AB_4 ,
        pad => A4(0)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = A19(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => A19(0)__PA ,
        oe => tmpOE__bufoe_9_net_0 ,
        fb => net_AB_19 ,
        pin_input => drive_AB_19 ,
        pad => A19(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = WDI(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => WDI(0)__PA ,
        pad => WDI(0)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = DB0(0)
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => DB0(0)__PA ,
        oe => tmpOE__bufoe_6_net_0 ,
        fb => net_DB_0 ,
        pin_input => Net_300 ,
        pad => DB0(0)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = CLK2MHZ(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => CLK2MHZ(0)__PA ,
        pin_input => Net_20 ,
        pad => CLK2MHZ(0)_PAD );
    Properties:
    {
    }

ARM group 0: empty
CAN group 0: empty
Cache group 0: empty
CapSense group 0: empty
Clock group 0: 
    Clock Block @ F(Clock,0): 
    clockblockcell: Name =ClockBlock
        PORT MAP (
            imo => ClockBlock_IMO ,
            pllout => ClockBlock_PLL_OUT ,
            ilo => ClockBlock_ILO ,
            clk_100k => ClockBlock_100k ,
            clk_1k => ClockBlock_1k ,
            clk_32k => ClockBlock_32k ,
            xtal => ClockBlock_XTAL ,
            clk_32k_xtal => ClockBlock_XTAL_32KHZ ,
            clk_sync => ClockBlock_MASTER_CLK ,
            clk_bus_glb => ClockBlock_BUS_CLK ,
            clk_bus => ClockBlock_BUS_CLK_local );
        Properties:
        {
        }
Comparator group 0: empty
DFB group 0: empty
DSM group 0: empty
Decimator group 0: empty
EMIF group 0: empty
I2C group 0: empty
LCD group 0: empty
LVD group 0: empty
PICU group 0: empty
PM group 0: empty
SC group 0: empty
SPC group 0: empty
Timer group 0: empty
USB group 0: empty
VIDAC group 0: empty
OpAmp group 0: empty
CsAbuf group 0: empty
Vref group 0: empty
LPF group 0: empty
SAR group 0: empty
ANAIF group 0: empty
PHUB group 0: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |               | 
Port | Pin | Fixed |      Type |       Drive Mode |          Name | Connections
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   0 |   0 |       |      NONE |     HI_Z_DIGITAL |        A11(0) | FB(net_AB_11), In(drive_AB_11), OE(tmpOE__bufoe_9_net_0)
     |   1 |       |      NONE |     HI_Z_DIGITAL |         A8(0) | FB(net_AB_8), In(drive_AB_8), OE(tmpOE__bufoe_9_net_0)
     |   2 |       |      NONE |     HI_Z_DIGITAL |        DB3(0) | FB(net_DB_3), In(Net_328), OE(tmpOE__bufoe_6_net_0)
     |   3 |       |      NONE |     HI_Z_DIGITAL |       nIOE(0) | FB(net_nIOE), In(drive_nIOE), OE(tmpOE__bufoe_9_net_0)
     |   4 |       |      NONE |     HI_Z_DIGITAL |        A14(0) | FB(net_AB_14), In(drive_AB_14), OE(tmpOE__bufoe_9_net_0)
     |   5 |       |      NONE |     HI_Z_DIGITAL |         A6(0) | FB(net_AB_6), In(drive_AB_6), OE(tmpOE__bufoe_9_net_0)
     |   6 |       |      NONE |     HI_Z_DIGITAL |        DB2(0) | FB(net_DB_2), In(Net_312), OE(tmpOE__bufoe_6_net_0)
     |   7 |       |      NONE |     HI_Z_DIGITAL |        A15(0) | FB(net_AB_15), In(drive_AB_15), OE(tmpOE__bufoe_9_net_0)
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   1 |   2 |     * |      NONE |      RES_PULL_UP | Button_Pin(0) | 
     |   4 |       |      NONE |     HI_Z_DIGITAL |        LIR(0) | 
     |   5 |       |      NONE |         CMOS_OUT |      nWAIT(0) | 
     |   6 |       |      NONE |     HI_Z_DIGITAL |         ST(0) | 
     |   7 |       |      NONE |         CMOS_OUT |      nINT0(0) | In(Net_499)
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   2 |   1 |       |      NONE |     HI_Z_DIGITAL |        A17(0) | FB(net_AB_17), In(drive_AB_17), OE(tmpOE__bufoe_9_net_0)
     |   2 |       |      NONE |         CMOS_OUT |    nRAMCS0(0) | In(Net_99)
     |   3 |       |      NONE |     HI_Z_DIGITAL |     nRESET(0) | FB(Net_30)
     |   4 |       |      NONE |     HI_Z_DIGITAL |         A5(0) | FB(net_AB_5), In(drive_AB_5), OE(tmpOE__bufoe_9_net_0)
     |   5 |       |      NONE |     HI_Z_DIGITAL |         A7(0) | FB(net_AB_7), In(drive_AB_7), OE(tmpOE__bufoe_9_net_0)
     |   6 |       |      NONE |     HI_Z_DIGITAL |        phi(0) | FB(Net_16)
     |   7 |       |      NONE |     HI_Z_DIGITAL |    nBUSACK(0) | 
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   3 |   1 |       |      NONE |         CMOS_OUT |    nRAMCS1(0) | In(Net_102)
     |   2 |       |      NONE |     HI_Z_DIGITAL |        DB5(0) | FB(net_DB_5), In(Net_332), OE(tmpOE__bufoe_6_net_0)
     |   3 |       |      NONE |     HI_Z_DIGITAL |        A18(0) | FB(net_AB_18), In(drive_AB_18), OE(tmpOE__bufoe_9_net_0)
     |   4 |       |      NONE |     HI_Z_DIGITAL |         A2(0) | FB(net_AB_2), In(drive_AB_2), OE(tmpOE__bufoe_9_net_0)
     |   5 |       |      NONE |     HI_Z_DIGITAL |        nRD(0) | FB(net_nRD), In(drive_nRD), OE(tmpOE__bufoe_9_net_0)
     |   6 |       |      NONE |     HI_Z_DIGITAL |        nWR(0) | FB(net_nWR), In(drive_nWR), OE(tmpOE__bufoe_9_net_0)
     |   7 |       |      NONE |     HI_Z_DIGITAL |      nHALT(0) | 
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   4 |   0 |       |      NONE |     HI_Z_DIGITAL |        DB7(0) | FB(net_DB_7), In(Net_336), OE(tmpOE__bufoe_6_net_0)
     |   1 |       |      NONE |     HI_Z_DIGITAL |        A10(0) | FB(net_AB_10), In(drive_AB_10), OE(tmpOE__bufoe_9_net_0)
     |   2 |       |      NONE |     HI_Z_DIGITAL |        A13(0) | FB(net_AB_13), In(drive_AB_13), OE(tmpOE__bufoe_9_net_0)
     |   3 |       |      NONE |     HI_Z_DIGITAL |        A12(0) | FB(net_AB_12), In(drive_AB_12), OE(tmpOE__bufoe_9_net_0)
     |   5 |       |      NONE |     HI_Z_DIGITAL |        DB6(0) | FB(net_DB_6), In(Net_320), OE(tmpOE__bufoe_6_net_0)
     |   6 |       |      NONE |     HI_Z_DIGITAL |        A16(0) | FB(net_AB_16), In(drive_AB_16), OE(tmpOE__bufoe_9_net_0)
     |   7 |       |      NONE |     HI_Z_DIGITAL |        DB4(0) | FB(net_DB_4), In(Net_316), OE(tmpOE__bufoe_6_net_0)
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   5 |   2 |       |      NONE |     HI_Z_DIGITAL |        nME(0) | FB(net_nME), In(drive_nME), OE(tmpOE__bufoe_9_net_0)
     |   4 |       |      NONE |         CMOS_OUT |    nBUSREQ(0) | 
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
   6 |   0 |       |      NONE |     HI_Z_DIGITAL |         A0(0) | FB(net_AB_0), In(drive_AB_0), OE(tmpOE__bufoe_9_net_0)
     |   1 |       |      NONE |     HI_Z_DIGITAL |        DB1(0) | FB(net_DB_1), In(Net_324), OE(tmpOE__bufoe_6_net_0)
     |   7 |     * |      NONE |         CMOS_OUT |    LED_Pin(0) | 
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
  12 |   2 |       |      NONE |     HI_Z_DIGITAL |         A1(0) | FB(net_AB_1), In(drive_AB_1), OE(tmpOE__bufoe_9_net_0)
     |   3 |       |      NONE |     HI_Z_DIGITAL |         A9(0) | FB(net_AB_9), In(drive_AB_9), OE(tmpOE__bufoe_9_net_0)
-----+-----+-------+-----------+------------------+---------------+---------------------------------------------------------
  15 |   0 |       |      NONE |     HI_Z_DIGITAL |         A3(0) | FB(net_AB_3), In(drive_AB_3), OE(tmpOE__bufoe_9_net_0)
     |   1 |       |      NONE |         CMOS_OUT |     nROMCS(0) | In(Net_94)
     |   2 |       |      NONE |     HI_Z_DIGITAL |         A4(0) | FB(net_AB_4), In(drive_AB_4), OE(tmpOE__bufoe_9_net_0)
     |   3 |       |      NONE |     HI_Z_DIGITAL |        A19(0) | FB(net_AB_19), In(drive_AB_19), OE(tmpOE__bufoe_9_net_0)
     |   4 |       |      NONE |         CMOS_OUT |        WDI(0) | 
     |   5 |       |      NONE |     HI_Z_DIGITAL |        DB0(0) | FB(net_DB_0), In(Net_300), OE(tmpOE__bufoe_6_net_0)
     |   6 |       |      NONE |         CMOS_OUT |    CLK2MHZ(0) | In(Net_20)
----------------------------------------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 10s.277ms
Digital Placement phase: Elapsed time ==> 19s.929ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
"C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "URSO180GLUESoC2_r.vh2" --pcf-path "URSO180GLUESoC2.pco" --des-name "URSO180GLUESoC2" --dsf-path "URSO180GLUESoC2.dsf" --sdc-path "URSO180GLUESoC2.sdc" --lib-path "URSO180GLUESoC2_r.lib"
Routing successful.
Digital Routing phase: Elapsed time ==> 20s.436ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 37s.192ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.053ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Warning: sta.M0019: URSO180GLUESoC2.rpt: Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at Net_499_split/main_0 --> Net_499_split/q  (File=P:\Projects\PuProjects\URSO180\Hardware\Glue_Logic\FreeSoC2\URSO180GLUESoC2.cydsn\URSO180GLUESoC2.rpt)
Timing report is in URSO180GLUESoC2_timing.html.
Static timing analysis phase: Elapsed time ==> 2s.008ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.001ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.348ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 93s.974ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 93s.975ms
API generation phase: Elapsed time ==> 66s.959ms
Dependency generation phase: Elapsed time ==> 1s.608ms
Cleanup phase: Elapsed time ==> 0s.015ms
