Active-HDL
Active-HDL Student Edition has a load-and-go type of license mechanism. This will allow students to use the tool immediately after the installation. They do not have to register the product in order to get the license. However, Active-HDL Student Edition build has the validity until December 31, 2015. After the build is expired, the latest release of Student Edition can be downloaded from the Aldec web site by simply registering yourself.
Active-HDL Student Edition is limited in terms of features in comparison to a commercial version of Active-HDL. Refer to the Limitations of the Student Edition section for details.
The following is a brief overview of new features and changes introduced to the commercial version of Active-HDL 9.3:
Active-HDL 9.3 requires validation of your existing maintenance contract. The latest version requires a valid maintenance contract as of 10/1/2013. For additional information refer to the Licensing chapter.
Active-HDL requires FlexNet ver.11.9.1.
The ALDEC_LICENSE_FILE system variable is no longer set during the installation of Active-HDL. Note however that if the variable is set manually, it is still supported. (SPT65981)
NOTE:
Due to internal changes in the compiler and simulator as well as updates
in third-party tool libraries, all user-defined libraries should be re-compiled
after the installation of Active-HDL 9.3. The installation program of
version 9.3 delivers and installs only the updated system
and vendor-specific libraries that do not require re-compilation after
Active-HDL is installed.
All existing designs will not have any problems associated with re-compiling
the libraries. If you update Active-HDL to version 9.3 and do not re-compile
your design libraries, the following error message will be displayed in
the Console window:
# ELBREAD: Warning: Files created by the old version of the compiler found.
# ELBREAD: Error: Library '<library_name>' has incompatible format.
Recompile all library units.
VHDL Compilation and Simulation
Support for VHDL 2008 (IEEE Std 1076
entity tb is (SPT60820)
|
Verilog Compilation and Simulation
Compilation and simulation of designs using selected
Altera
SystemVerilog Compilation and Simulation
Performance of timing simulation has been significantly improved.
The string concatenation has been optimized.
Traversal method arguments which are smaller than the size of the corresponding array index type are properly detected.
Constants of the event type are supported.
Support for Verilog Configuration units has been
added. Configurations can be used to specify design settings, help in
source code debugging and switch among various description types of the
same component. For more information, refer to IEEE Std 1800
The arrays of unpacked structures are supported. (SPT62535, SPT64760)
Assignments to concatenations which consist of automatic and external variables are supported. (SPT66406)
reg [10:0] r1;
task automatic t1();
reg [10:0] r2;
{ r1, r2 } = 1;
endtask
Modport expressions are supported. For more information, refer to the Modports section of the SystemVerilog Reference Guide. (SPT60906, SPT64759)
Assignment of queues with the concatenation operator is supported. (SPT63921, SPT66659)
The unpacked array concatenation for queues and dynamic arrays is supported. (SPT61249, SPT66815)
Support for the argument of a structure type used in the $past function has been added. (SPT62514)
A selection from an array of instances with an index expression containing variables is supported. (SPT64692)
interface iface;
endinterface
virtual iface readPort;
iface ii[10]();
initial
for(int i=0 ; i<10; i++) begin
readPort = ii[i];
end
Declarations of ANSI style localparam used on the parameter port list of a unit are supported. (SPT64747)
module mod1
#(localparam H_B=3, L_B=0)
(input wire [H_B:L_B] in,
input wire clk, set, strb,
output logic [H_B:L_B] out);
endmodule
Casting one predefined unpacked structure type to another is supported.
typedef struct {logic [15 : 0] v [3];int r; } Ts1;
typedef struct {shortint vv [3]; integer rr;} Ts2;
Ts1 s1;
Ts2 s2;
initial s2 = Ts2'(s1);
The type operator for localparam constants is supported.
Templates of modules, interfaces and programs for the most common applications are supported. (SPT62537)
The error messages have been enhanced with the information about signals causing issues. (SPT64854)
The foreach iterative constraints are supported, for example:
class C;
rand logic [3:0] arr [15:5];
constraint array_constraint {
foreach(arr[i]) arr[i] inside {4'h1, 4'h2,4'ha,4'hb};
}
endclass
(SPT63596, SPT61722)
The assert, cover, and assume immediate assertion statements can be used inside the parameterized classes that have data types supplied as parameters.
The strong and weak sequence operators are supported.
The property operators: always, nexttime, until, and until_with are supported. The operators of the strong form: s_eventually, s_nexttime, s_until, s_until_with, the operators of the ranged form always[n:m], s_always[n:m], nexttime[n:m] and the operators of the ranged strong form: s_eventually[n:m], s_nexttime[n:m] are also supported.
The triggered method
of a named sequence is supported in the context
of the concurrent assertions. The method replaces the ended
method defined in IEEE Std 1364
The specparam constants can be declared in the module body without using the specify blocks.
The $monitor task working with fixed-size unpacked arrays was implemented.
The default behavior of calculating Covergroup
Coverage has been changed. Covergroup Coverage statistics are calculated
according to IEEE Std 1800
The anonymous programs are supported. For more
information, refer to IEEE Std 1800
A subset of functionality that includes modules, interfaces, and programs parameterized by a type was implemented. Variable declarations, subprograms, types, constants, procedural statements, interface modports, and initial and always processes are supported.
Support for the module port of the event type has been added. (SPT65043)
SystemVerilog Assertions
The first_match operator is supported. For more information, refer to the Sequences section of the SystemVerilog Reference Guide. (SPT14378, SPT62987, SPT66619)
The typed arguments in sequence and property declarations are partially supported. There is a limitation that the typed arguments cannot be of the property type.
The local variable formal arguments are supported in a sequence and in a property declaration.
Static function calls invoked from the property declaration are supported. (SPT67327)
The followed-by operators: #-# and #=# are supported.
Mixed-Language Compilation and Simulation
A VHDL port of the integer type can be mapped with a SystemVerilog port of the int or integer type or with any reg/net of 32-bit width. (SPT66165, SPT63170)
C/C++/SystemC Compilation and Simulation
The SystemC library version 2.3.0 is available.
It implements IEEE Std 1666
Starting with the 9.3 release, Active-HDL will support the three latest versions of Microsoft Visual Studio. Support for Visual Studio 11 has been added. Consequently, Visual Studio 8.0 is no longer supported. The *.lib files required for building SystemC applications with Visual Studio 8.0 will no longer be included in the installation.
Active-HDL 9.3 introduces the new coverage flow.
The new flow redefines the default coverage settings in order to improve
the simulation performance. Collecting the statistics on the total number
of hits was excluded from the defaults. In the current version, the reports
contain only the information whether a design unit/object included in
the report was hit without specifying the number of hits.
Additionally, some expression types are excluded from the default Expression
Coverage report. The expressions that are no longer covered by default
and counting of the total number of hits are still available and can be
enabled with the new -coverage_options argument
of the acom and alog
command.
The current version introduces the -coverage argument which allows selecting the coverages available in the design. The argument can be used instead of the -dbg, -exc, and -path arguments. It is recommended to collect the statistics to the ACDB database when using the -coverage and -coverage_options arguments. For more information, refer to the descriptions of the acom and alog commands.
Performance of Expression and Statement Coverage has been significantly improved.
The UCIS properties are supported by ACDB API.
The names of the ACDB API functions, structures, and definitions were changed to conform to the Accellera UCIS standard. Previously, the names began with the acdb prefix. In the current version, the ucis prefix is used.
Coverage Database
The size of generated ACDB files has been reduced. Consequently, the time of database generation has been also improved.
Due to the latest changes in the format of the ACDB database, the files generated by previous versions of the simulator cannot be opened in the current version of Active-HDL. Additionally, an error will be displayed in the Console when trying to open an ACDB database of an obsolete file format.
Code Coverage and Expression Coverage results can be saved to one ACDB file. (SPT50854, SPT47730)
Statement Coverage
Due to the latest changes in the implementation of the VHDL for loop statement, the way in which the Statement Coverage statistics for the loop are collected has been changed. In the previous version, the result for the for loop execution was the number of iterations in the loop parameter range. In the current implementation, an additional iteration checking if the loop parameter exceeded the range is included in the statistics. For that reason, the number of executions of the standalone for loop included in the coverage report is the number of the executions with the true condition increased by one.
Expression Coverage
Expression Coverage statistics can be saved to the ACDB database. In the current implementation of the coverage engine, statistics for expressions can be collected both for instances and individual design units (previously, statistics could be collected only for instances). The new implementation also introduces new command arguments that allow controlling all supported types of coverage. For additional information, refer to Scripts.
Expression Coverage results stored in an ACDB file can be included or excluded from the coverage statistics by using the -exc_include or -exc_exclude argument of the asim command, respectively. For more information refer to the description of the asim command.
Functional Coverage
Source code containing multidimensional packed arrays can be analyzed by Functional Coverage.
The Functional Coverage report is divided into the hierarchy and design units sections by default when the acdb report command is used. Previously, such sections were not available in the report. (SPT63398)
Coverage Reports
Presentation of statistics in coverage reports has changed. Previously, regions for which no coverage data was collected were denoted in gray in an HTML report. Starting from this version of Active-HDL such statistics are not presented. To add the information about regions with no coverage data to the report, pass the -shownodata argument to the syntax of the acdb report command. For additional information, refer to Scripts. (SPT66528)
The instances in the hierarchy tree of an HTML report are colored according to their coverage status. The fully covered or not completely covered instances are displayed in green or red, respectively.
The percentage values containing information about covered instances are displayed in the hierarchy tree of an HTML report. (SPT66527)
HDL source code can be observed directly from the Hierarchy tab in an HTML report window when checking the coverage results. (SPT67059)
Condition Coverage and Expression Coverage results collected in ACDB can be presented in an HTML report. (SPT63156, SPT66799)
The following updates have been introduced to the system and vendor-specific libraries:
New
Libraries
Verification Libraries
1.The Open Source VHDL Verification Methodology Library (OSVVM) has
been added. (SPT66208, SPT67057).
Implementation
1. Altera Quartus
2. Lattice
3. Microsemi Libero SoC 11.1 SP1 (SMARTFUSION2, SMARTFUSION2_VER)
4. Xilinx
Updated
Libraries
Verification Libraries
1. The Accellera's Open Verification Library (OVL) delivered with Active-HDL
($aldec\vlib\ovl) has been upgraded
to version 2.7.
HDL Synthesis
1. Synopsys
Implementation
1. Lattice ispLEVER Classic 1.7
2. Xilinx ISE
Location of Library
Files
1. The path to library source files and the directory structure of
vendor libraries has changed. Starting from the current version of Active-HDL,
the vendor libraries are stored in separate vendor folders. Additionally,
the libraries used in VHDL and Verilog simulation are installed to separate
subfolders of a vendor folder. For example, the VHDL library for the Altera
StratixV family is stored in the $aldec\vlib\altera\vhdl\stratixv
subfolder. Previously, this library was installed to the $aldec\vlib\stratixv
directory. (SPT49412)
2. Xilinx SECUREIP library is installed to the $aldec\\vlib\xilinx_ise\verilog\secureip
and/or $aldec\vlib\xilinx_vivado\verilog\secureip
folder (depending on a library vendor selected during the installation).
NOTE: For additional information about availability of discontinued libraries, please contact Aldec Technical Support at http://www.aldec.com/support. Please note, you will be asked to register if you have not already.
New Flowcharts
HDL Synthesis
1. Altera Quartus II 12.1 Synthesis & Implementation (supports
Quartus II 12.1 SP1)
2. Altera Quartus II 13.0 Synthesis & Implementation (supports
Quartus II 13.0 SP1)
3. Synopsys Synplify
4. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design
Planner H-2013.03 (supports FPGA Synthesis H-2013.03 SP1)
5. Synopsys Synplify Pro F-2011.09/2012.03 for Actel/Microsemi (supports
Synplify Pro F-2012.03MSP1)
6. Synopsys Synplify Pro H-2013.03 for Actel/Microsemi (supports Synplify
Pro H-2013.03M-1)
7. Synopsys Synplify Pro G-2012.09 for Lattice (supports Synplify Pro
G-2012.09L-SP1)
8. Lattice Diamond LSE 2.1
9. Lattice Diamond LSE 2.2
10. Lattice Synthesis & Implementation in Diamond 2.1
11. Lattice Synthesis & Implementation in Diamond 2.2
12. Xilinx ISE/WebPack 14.3 Synthesis & Implementation
13. Xilinx ISE/WebPack 14.4 Synthesis & Implementation
14. Xilinx ISE/WebPack 14.3 XST VHDL/Verilog (SPT65448)
15. Xilinx ISE/WebPack 14.4 XST VHDL/Verilog
16. Xilinx ISE/WebPack 14.5 XST VHDL/Verilog
17. Xilinx ISE/WebPack 14.6 XST VHDL/Verilog
18. Xilinx Vivado 2012.3 Synthesis
19. Xilinx Vivado 2012.4 Synthesis (supports Vivado 2012.4.1)
20. Xilinx Vivado 2013.1 Synthesis
21. Xilinx Vivado 2013.2 Synthesis
22. Xilinx Vivado 2012.3 Synthesis & Implementation
23. Xilinx Vivado 2012.4 Synthesis & Implementation (supports Vivado
2012.4.1)
24. Xilinx Vivado 2013.1 Synthesis & Implementation
25. Xilinx Vivado 2013.2 Synthesis & Implementation
Physical Synthesis
1. Xilinx PlanAhead 14.3
2. Xilinx PlanAhead 14.4 (supports PlanAhead 14.4.1)
3. Xilinx PlanAhead 14.5
4. Xilinx PlanAhead 14.6
Implementation
1. Actel/Microsemi Designer 10.0/10.1 (supports Designer 10.1 SP2)
2. Actel/Microsemi Designer 11.0/11.1
3. Altera Quartus II 12.1 (supports Quartus II 12.1 SP1) (SPT65493)
4. Altera Quartus II 13.0 (supports Quartus II 13.0 SP1) (SPT67075)
5. Lattice Diamond 2.1
6. Lattice Diamond 2.2
7. Xilinx ISE/WebPack 14.3
8. Xilinx ISE/WebPack 14.4
9. Xilinx ISE/WebPack 14.5
10. Xilinx ISE/WebPack 14.6
11. Xilinx Vivado 2012.3 (SPT65137)
12. Xilinx Vivado 2012.4 (supports Vivado 2012.4.1)
13. Xilinx Vivado 2013.1
14. Xilinx Vivado 2013.2
Updated Flowcharts
HDL Synthesis
1. Lattice Diamond LSE 2.0 (supports Diamond 2.0.1)
2. Lattice Synthesis & Implementation in Diamond 2.0 (supports
Diamond 2.0.1)
3. Mentor Graphics
Implementation
1. Lattice Diamond 2.0 (supports Diamond 2.0.1)
Flowchart Changes
and Improvements
Xilinx flowchart
1. The SmartXplorer Options
dialog box was enhanced with new buttons importing the settings from the
Implementation Options dialog
box to the fields: NGDBuild Options,
MAP Options, PAR
Options, and TRCE Options.
The buttons are located next to these fields and can be used to import
the settings related to each option separately. (SPT62878)
2. When one of SmartXplorer strategies is applied, either by the user
or automatically, the options in the
Implementation Options dialog box are no longer reset to the default
settings. Previously, all implementation options were reset prior to applying
SmartXplorer strategy.
3. Starting from Xilinx ISE/WebPack 14.4, the Tool.ini
file which stores option settings for Xilinx tools, has been renamed to
Flowtools.ini and moved to \$dsn folder. (SPT66030)
NOTE: For additional information about availability of discontinued flowcharts, please contact Aldec Technical Support at http://www.aldec.com/support. Please note, you will be asked to register if you have not already.
The Source column which displays paths to design files has been added to the Structure tab. To activate it, right-click the column header and select the Source implementation option. If the Source column is not completely visible, a tooltip with a full path to a design file is displayed.
Options related to design management previously available in separate entries of the Preferences dialog box have been rearranged and located within the Environment category. The new Design subcategory is divided into three groups of settings that allow defining a location of design folders for new source files added to a design (Structure), specifying generation settings for a design status report (Status), and specifying a startup script executed when a design is loaded or set as active (Startup Script). By default, all types of source files listed in the Structure category are added to the $dsn\src folder, the report files with the design status are saved to the $dsn\src\DESIGN_STATUS\<yyyy_mm_dd_hh_mm> folder (where <yyyy_mm_dd_hh_mm> points to the date and time of folder creation), and $dsn\design.do is the default startup script executed by Active-HDL whenever you open or change an active design. (SPT62127, SPT65058)
The Team category has been added to the Design Settings and Preferences dialog boxes. The options available in this category allow specifying the Team Settings file (*.adf) which can be used to override either the settings of the current active design or global preferences. For more information, refer to the description of the Team category in the Design Settings or Preferences dialog box.
The Stop elaboration if a component cannot be bound option, the equivalent of the -unbounderror argument of the asim command, has been added to the Simulation | VHDL category of the Design Settings dialog box. The new option can be used to terminate initialization of simulation if an unbound component is detected during elaboration of a VHDL or EDIF design. (SPT65720)
The default standard for SystemVerilog sources
(files with the *.sv extension) set while adding files to a design is
different in Active-HDL 9.3 than the standard set by default in the previous
releases. Currently, the SystemVerilog source files inherit the standard
from the design settings. Previously, the IEEE Std 1800
The Do not create design directory option has been added to the New Design Wizard window. If the option is enabled, the design folder will not be created and all design files will be stored in the location displayed in the Design file path. Equivalent to the createdesign command with the -nodesdir argument.
The location of all undocked documents is restored when loading a workspace. They will be opened in the same place in which they were located when a workspace was closed. Note that a waveform document has to be saved as a Waveform View Configuration file (*.awc) in order to be loaded when opening a workspace. (SPT67384)
The Zoom In and Zoom Out operations can be activated by using Ctrl+Num+ and Ctrl+Num-. (SPT66500)
The block editing has been implemented. To activate it, enter the Column Selection Mode, select an appropriate block of text and enter a new string which will replace the appropriate lines in the selected block. (SPT61989, SPT64598)
The default design unit header defined in the Design Unit tab of the Code Generation Settings dialog box has been supplemented with new entries that allow controlling the use of packages defining the SIGNED and UNSIGNED types (IEEE.std_logic_arith.all, IEEE.std_logic_signed.all, and IEEE.std_logic_unsigned.all). Previously, the use of these packages could not be controlled. (SPT65313, SPT65032)
The format of a block diagram sheet can be enlarged to size A2, A1, or A0. The size of the block diagram can be selected in the Page Size tab of the Page Setup dialog box. (SPT65415)
Support for the GIF, PNG, JPG, and 32-bit BMP format was added. Transparent images are also supported. (SPT65416, SPT65417)
The names of newly created nets can be shown while drawing new connections or connecting new nets to existing wires or buses. To enable this feature, the Show names of newly created nets option should be checked in the preferences of the Block Diagram Editor. (SPT66027)
New options, which allow modifying the compound bus settings, have been added to the General tab of the Bus Properties dialog box. The options can be used to define the index range, type, or delay of the selected signals used by the compound bus which is displayed as a thick orange line on the diagram. (SPT61862)
Symbol shapes and pin locations can be easily modified without entering the Edit Symbol Mode. The symbols can be resized by dragging a red frame surrounding a symbol in the places marked by black squares. To change the pin location, select a wire or bus connected to the pin at its very end and drag the bus or wire along the symbol border. The changes will be saved to a library once you select the Update Symbols option from the Design menu or the Save Symbols to Library option available from the context menu of the block diagram document in the Design Browser window. For more information, see the description of the Editing without Entering Edit Symbol Mode section in the Editing Symbols and Fubs topic. (SPT65422, SPT65431)
A new feature which allows increasing the number of wire indexes in the bus taps has been added. To use it, copy the wires with their bus taps and select the Paste Special option from the context menu or press Ctrl+Shift+V. In the Paste Special dialog box, choose Increment wire indexes. If you do not want to increment the number of wire indexes in the bus taps, select the Keep wire indexes unchanged option. (SPT49830)
The User Defined and Unconnected mapping types have been added to the Mapping Type column in the Symbol Properties dialog box. The first one can be used to manually define the mapping whereas the latter disables the Design Rule Check (DRC) for ports which were intentionally left unconnected, which prevents from receiving a warning during code generation. For more information, refer to the description of the Port Mapping tab of the Symbol Properties dialog box. (SPT66584)
The initial letter instead of a full name of the mapping specified in the Mapping Type column of the Symbol Properties dialog box is displayed on a block diagram document. (SPT66757)
The format of the block diagram documents has been upgraded to version 1.04. The block diagram files created in the current version cannot be opened in the previous versions of the Block Diagram Editor.
The default generation style in VHDL was changed from the one-process to two-processes template.
The Delay object has been enhanced with a new property: Immediate Exit Condition. If the immediate exit condition is met before the delay time specified for the Delay object, the machine exits the delay state. The new condition can be set in the Delay Properties dialog box. (SPT61857)
The default distance between the symbols on the state diagrams automatically generated by the Code2Graphics converter and the default size of the state, junction, and delay symbol can be customized. The default settings can be customized in the Preferences dialog box. (SPT62209)
Support for the GIF, PNG, JPG, and 32-bit BMP format was added. Transparent images are also supported. (SPT65416, SPT65417)
The format of the state diagram documents has been upgraded to version 1.28. The state diagram files created in the current version cannot be opened in the previous versions of the State Diagram Editor.
The relative position of an object can be set so that it is possible to decide whether an object should be placed above or below other objects on a state diagram. This can be done with the new Bring to Top and Bring to Bottom options available from the context menu. For additional information, refer to the State Diagram Object Visibility section in the State Diagram Editor topic.
The global preferences of the waveform viewer have been moved from the stand-alone Waveform Preferences dialog box and integrated with the Active-HDL framework. The waveform preferences are available in the Editors | Waveform Viewer/Editor | Accelerated Waveform Viewer subcategory of the Preferences dialog box. (SPT65200)
The viewer allows synchronizing the view with simulation results not only among Waveform or List View panes but also in all open waveform documents. By relocating the active cursor in one document, it is possible to follow signal waves in the others. Synchronization can be enabled by using the Synchronize Waveforms option in the Behavior | Basic subcategory of the waveform preferences. When it is on, the active cursors in individual waveforms are synchronized and relocated to the same position (time). If you relocate the active cursor in one waveform, the view in other waveform windows will be automatically scrolled forward or backward to the same simulation time. The Offset of synchronized cursor in % of waveform pane when scrolling horizontally option specifies the distance between the active cursor and the boundary of the Waveform View pane (either left or right) which will be preserved when the cursor is moved due to synchronization with the active cursor in another waveform window. Additionally, if synchronization is turned on, the Waveform Viewer can automatically set and use the same zoom in all open waveform files. (SPT64599)
The arithmetic mean of all duty cycles (average duty cycle) can be measured by selecting the Average Duty Cycle option from the Measurement | Measurement unit submenu available in the context menu of the Waveform View pane. For more information, refer to the description of the Measurements section in the Accelerated Waveform Viewer Window topic. (SPT66475)
It is possible to save the exact location of the timing cursor with the Save to Macro option available from the Waveform menu. Previously, the position of the cursor could be rounded. (SPT66715)
The current view in the waveform is retained after restarting the simulation if the Jump to simulation time option is disabled in the Behavior | Basic subcategory of the waveform preferences. (SPT62501, SPT19790)
The analog display mode is available for vectors of any width. Previously, this mode was available only for vectors up to 62 bits. (SPT67273, SPT62321)
The color of a named row can be set by using the Virtual signal color option in the Appearance category of the Preferences dialog box. (SPT51033)
The Zoom In and Zoom Out operations can be activated by using Ctrl+Num+ and Ctrl+Num-. (SPT66252)
The Zoom Mode can be temporarily activated either by pressing and holding the middle-mouse button or by holding the Ctrl key and the left-mouse button. Then, moving the mouse will select the area to be zoomed in. (SPT65699)
Selected waveform areas can be exported to graphics, PDF, HTML, and printed. The areas, also called marks, can be created, edited and removed in the Mark Mode. To display them in other modes, use the Show Marks option. All areas from the current waveform view are visible in the Marks List window. For more information, refer to the Marks section in the Accelerated Waveform Viewer Window topic. (SPT49949)
Selecting the object in the Waveform View pane highlights it in the Signal Grid pane. (SPT64291)
Support for the Waveform Comparison file (*.asdbc), which stores the differences between two simulation database files (*.asdb), has been added. It can be created only by comparing the simulation databases with the asdbcompare command (for more information, refer to the Scripts section). In addition, a Waveform Configuration file (*.awc) may be used to configure the Waveform Comparison file. (SPT21428)
The Connect to submenu has been added to the Waveform menu and to the context menu in the Accelerated Waveform Viewer window in the Signal Grid pane. The options available in the submenu allow connecting the waveform to the Accelerated Waveform Configuration file (*.awc), Simulation Database file (*.asdb), or Waveform Comparison file (*.asdbc). Additionally, the Connect to Simulator option has been moved to the Connect to submenu and the name of the option has been changed to Simulation. (SPT66017)
The floating-point radix with several new options supporting floating-point values has been added to the General tab of the Signal Properties dialog box. The tab has been divided into the Value Format and Floating Value Format subtab which contains the following options: Floating encoding, Floating notation, Precision, and Rounding method. (SPT62230, SPT64809)
The binary point is automatically set for the VHDL signals of the sfixed and ufixed types defined in the fixed_pkg package of the IEEE library. Basing on the range of the signal, the position of the binary point is set after the element whose index is equal to 0. In this way, the integer value is specified by the elements with positive indexes whereas the fractional value is defined by the elements with negative indexes. In addition, the notation of signals of the sfixed and ufixed type is set to signed 2's complement and unsigned, respectively. (SPT62701)
The contents of the Advanced Dataflow window can be printed. (SPT20954, SPT64492)
The following changes have been introduced to the Active-HDL macro commands:
The new coverage types are supported and can be selected by using the -cov argument of the acdb clear, acdb disable, acdb enable, acdb exclude, acdb include, acdb report, acdb_merge, and acdb_save commands. Except for Statement, Branch, and Functional Coverage, the argument also allows controlling and manipulating Expression Coverage (e) and Condition Coverage (c) statistics.
The -verbose argument has been added to the following commands: acdb clear, acdb disable, acdb enable, acdb exclude, acdb include, and acdb report. The argument enables the verbose mode which activates printing warning messages to the Console. If the argument is not specified, all warnings are omitted.
Wildcards in file names specified by the -i argument of the acdb merge command are supported.
The -nodetails argument has been added to the acdb report command. The argument generates the coverage report consisting only of the summary section. (SPT65893)
The -replace_path argument has been added to the syntax of the acdb report command. The new argument can be helpful in generating a report after a design containing a database file (.asdb) was relocated to a new directory. In this case, the argument can be used to replace original paths to HDL source files with their current location.
The -shownodata argument has been added to the syntax of the acdb report command. When the new argument is passed, a coverage report will also show instances and design units even if they do not contain statements or expressions/conditions for which coverage data could be collected.
The -uncovered argument has been added to the syntax of the acdb report command. When the new argument is passed, the coverage report omits the details for covered statements and focuses on those portions of source code that have not yet been examined by a testbench.
The control over the coverage types available in the design is combined into the new -coverage argument for the acom and alog commands which can be used instead of the -dbg, -exc and -path arguments. The use of the -dbg, -exc and -path arguments to enable coverages is still possible but the use of the -coverage argument is recommended.
The -coverage_options argument for the acom and alog commands defines whether the number of successful passes has to be included in the statistics and whether to include or exclude certain types of expressions from the Expression Coverage. For more information, refer to the descriptions of the acom and alog commands.
The activehdlteam command has been added. It allows setting the options for the Team Settings file (*.adf). The command is equivalent to the options available in the Team category of the Design Settings and Preferences dialog boxes. For more information, refer to the description of the activehdlteam command.
The behavior of the amap -del command has changed. Since Active-HDL 9.3, to detach a global library, the -global argument needs to be specified.
The -asdbc <asdbc_file> argument has been added to the syntax of the asdbcompare command. The new argument allows saving the comparison results of two simulation database files (*.asdb) into the Waveform Comparison file (*.asdbc). (SPT21428)
The -strobe -signal argument can be passed multiple times in the syntax of the asdb2ctf command. Previously, only one strobe signal could be specified. (SPT64628)
The -comparison argument has been added to the syntax of the asdbman info command. The new argument allows creating a comparison report from the specified Waveform Comparison file (*.asdbc).
The -replace_no_data argument has been implemented in the asdbman merge command. The new argument replaces the No data areas in a history of signal values while merging simulation databases.
The -acdb_cov argument of the asim command has been extended with the new parameters. The argument allows specifying newly supported types of coverage data that can be collected during simulation, that is, statistics for Expression Coverage (e) and Condition Coverage (c).
The -asdbtemp <path> argument has been added to the asim command. The argument can improve simulation performance when signals are logged to an ASDB file located on a network drive. For more information, refer to the description of the asim command.
The -cvgmergeinstances and -cvgperinstance arguments were added to the asim command. The arguments allow collecting detailed coverage results without modifying the source code. For more information, refer to the description of the asim command.
The -immediate and -concurrent arguments have been added to the syntax of the assertion pass and assertion fail commands. The new arguments specify whether the command should count and report passes and failures of immediate or concurrent assertions.
The -immediate argument has been introduced to the syntax of the assertion report and cover report commands. When the new argument is passed, a report with coverage data is supplemented with statistics for expressions of immediate assert and cover statements, respectively.
The importdesignstructure command has been implemented. The command allows importing the structure of design folders created with an older version of Active-HDL.
The -fullverbose argument has been added to the syntax of the assertion report and cover report commands. The new argument creates a report containing all details and statistics collected for assertions and covers during simulation. Previously, such data was available only in the Assertions and Covers tab of the Assertion Viewer window.
The arguments: -extra, -vacuous, and -nonvacuous have been added to the ba and bad commands. The arguments are intended to be used along with the -failed and -passed arguments to specify behavior of an assertion breakpoint that is enabled or disabled. For example, the following command will enable the breakpoint that stops simulation if the /tb/UUT/assert_test assertion passes nonvacuously:
ba /tb/UUT/assert_test -passed -nonvacuous
The following command will disable breakpoints for all assertions that evaluate with extra failures or passes:
bad -all -failed -extra -passed
The @<cmd_file> argument of the ccomp command is no longer available and it has been replaced by the -f <cmd_file> argument.
The -immediate and -concurrent arguments have been added to the syntax of the cover command. The new arguments specify whether the command should count and report statistics for immediate and concurrent statements.
The designstatus macro command has been introduced. The new command can be used to generate a design status report to a user-defined folder. The location of the report files can be also determined globally for Active-HDL in the Preferences dialog box. (SPT48776)
The -change argument has been added to the excoverage command. The argument activates the change mode which allows modifying existing coverage data. For more information, refer to the description of the excoverage command.
The -mem argument of the find macro allows searching not only for Verilog memories but it also extends the command to search for VHDL constructs that model memories. For more information, refer to the description of the find command. (SPT65489)
The -c argument has been introduced to the syntax of the importmodelsim command. The new argument creates local copies of imported files. (SPT64467)
The average_duty_cycle argument has been added to the syntax of the measurement set command. The argument is equivalent to the Average Duty Cycle option available in the Measurement | Measurement Unit submenu available from the context menu of the Waveform View pane.
The simstats macro has been implemented. The new command prints to the Console detailed performance-related statistics about elaboration, simulation, memory allocation, CPU usage, etc. (SPT60939, SPT65014)
The -precision, -floatingnotation, -floatingencoding, and -rounding arguments have been added to the wave and wavevalueformat commands. The new arguments specify the format and the rounding method for floating-point values.
New commands have been added to control marks in the Accelerated Waveform window. The wavearea command creates a new area or overwrites an existing one, if the -overwrite argument is used. The wavearearemove command removes the specified area or all empty areas, if the -empty argument is used. To remove all defined areas in the active Waveform Viewer, use the wavearearemoveall command. (SPT49949)
The -align argument has been added to the syntax of the wavecolumn command. The new argument allows aligning the contents of the selected column in the active waveform window.
The wavecolumndump macro has been implemented. The command allows dumping the configuration of all columns of the active Accelerated Waveform Viewer window to the console.
The -tolreal and -expand arguments have been added to the syntax of the wavecompare command. The first argument is a counterpart of the same argument in the asdbcompare command and the latter is equivalent to the Expand hierarchy name option available in the Compare waveforms dialog box. The arguments are supported only in the Accelerated Waveform Viewer.
The -sourcehierarchy and -targethierarchy arguments of the wavecompare command are supported in the Accelerated Waveform Viewer.
The waveconnect command has been enhanced. The command supports the connection to the Accelerated Waveform Configuration file (*.awc), Simulation Database file (*.asdb), or Waveform Comparison file (*.asdbc).
The waveloadschema macro has been implemented. The command imports the color and font settings of the Accelerated Waveform Viewer from the Waveform Scheme file (*.wfs).
The following changes have been introduced to the environment of the Tcl interpreter:
The Tcl interpreter embedded in Active-HDL has been updated to version 8.5.12. Previously, Active-HDL used version 8.4.19.
The Tcllib package has been upgraded to version 1.14. (SPT65576)
The registry Tcl package has been added to Active-HDL. (SPT65392)
The following changes have been introduced to the environment of the Perl interpreter:
The Perl programming language embedded into the Active-HDL package has been updated to version 5.16.3. Previously, Active-HDL used version 5.003_07.
The following changes have been introduced to the predefined Active-HDL environment variables:
The new $curdocline and $curdoccolumn variables have been introduced. The former returns a line number of the currently edited document while the latter points to a number of a column in the currently edited document. (SPT65523)
The $ver variable has been renamed to $version.
The protectip detects when an encryption envelope
is not completed in a VHDL file with an appropriate pragma. According
to IEEE Std 1076
The following changes and improvements have been made to the import of third-party projects (File | Import):
The Altera Quartus II Project option allows importing projects coming from Quartus II 11.1 and 12.0.
The import of a ModelSim
The Xilinx ISE Project option allows importing projects coming from versions 13.3, 13.4, 14.1, and, 14.2 of Xilinx ISE.
The following changes and improvements have been made to the built-in Active-HDL simulation interfaces:
VPI
1. New SystemVerilog constructs (for example programs, packages, classes)
are supported.
2. Support for SystemVerilog types has been added.
The following improvements have been made to the Active-HDL wizards:
Export to HTML
Wizard
1. The starting page of the exported HTML project is automatically
displayed after it is generated if the Open
starting page in browser option is selected in the first step of
the HTML wizard.
2. The Include design hierarchy
option, available in the second step of the HTML wizard, allows exporting
the design hierarchy provided that a top-level unit has been selected.
The following changes and improvements have been made to the built-in third-party interfaces:
Spec-TRACER Requirements
Lifecycle Management system
Spec-TRACER is a complete Requirements Lifecycle Management system
targeting Mil/Aero designs that require DO-254 compliance. Spec-TRACER
facilitates different activities related to requirements including capture,
analysis, specification, verification, traceability, reviews/audits, management,
and reuse. The tool helps companies streamline a requirement engineering
process to better manage the development cycle, improve collaboration,
mitigate risk, track changes, and reduce costs. Active-HDL allows presenting
and tracing project elements in the Spec-TRACER
window. Additionally, it also allows capturing the test results basing
on simulation results stored in text files, creating associations among
requirements and test scenarios by using the tags inserted into files.
The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:
Interface to
Simulink
1. Support for the additional top-level modules during co-simulation
has been added. For more information, see the related note in the Running
Co-simulation topic in the Simulink Interface chapter.
2. The ald_do function has been enhanced
with the following arguments: resp, auto_start,
and path. The new arguments fulfill the requirements
of using the MATLAB Interface as a master program. For more information,
see Controlling Active-HDL from within MATLAB/Simulink Environment.
Interface
to MATLAB
1. The MATLAB interface supports flow with MATLAB acting as a master
program. Active-HDL can be started from MATLAB and execute designs with
MATLAB interface code. It allows creating robust testbench scenarios with
extensive math data analysis of multiple HDL simulation runs within one
MATLAB instance. The existing designs do not have to be modified in order
to be used in the new flow. (SPT64018)
2. The MATLAB interface has been reconstructed in order to support
TCP/IP based communication instead of a COM interface utilized in the
previous versions of Active-HDL. Registering the COM server with the matlab /regserver command is no longer required
during the Active-HDL installation process.
3. MATLAB is no longer automatically closed when the co-simulation
session is finished. The change makes automated testing scenarios more
flexible especially when several sessions are going to be run and MATLAB
is invoked once at the beginning of scenario. The ml_quit
routine/task has been introduced to close MATLAB when the entire test
is completed.
4. The complex variables like structure fields or array indexes are
supported by the get_variable() and get_item()
routines. (SPT64028)
5. The get_variable() routine supports getting
value of expression passed to the MATLAB environment.
6. The ml2hdl() routine allows reusing the
existing array identifier for subsequent ml2hdl()
calls. The routine has an optional parameter pointing to the existing
array which is replaced by the ml2hdl() routine.
(SPT64057)
7. The severity of errors can be specified so that the user can decide
whether the simulation should stop, terminate or continue when an error
related to the MATLAB interface occurs. The severity can be set with the
-err_severity argument of the ml_setup()
command or with the routines called from HDL source code. These routines
are ml_onerror() and $ml_onerror()
for the VHDL and SystemVerilog languages, respectively.
8. The ml_pathdef_dir() function and the
pathdef_dir argument of the ml_setup()
function have been introduced. These utilities allow specifying the path
to the local copy of the MATLAB Search Path file (pathdef.m).
The local copy of the file is created in order to register the Active-HDL
Toolbox in case when the user who installed Active-HDL has insufficient
permissions to modify the pathdef.m
file located in the MATLAB installation directory. In such case, the functions
should be used in HDL source code before passing any call to a routine
which communicates with the MATLAB environment so that the path to the
local pathdef.m file is known
before MATLAB starts.
9. The ml_start_dir() function and the start_dir argument for the ml_setup()
function that allow changing the MATLAB startup folder have been introduced.
10. The following MATLAB interface tasks: ml_quit
and eval_string can be used in the Console
or in a macro after loading the interface during co-simulation. The following
forms are available: ml_quit,
$ml_quit, eval_string("<matlab_expression>"),
and $eval_string("<matlab_expression>").
(SPT48184)
The Active-HDL Wizards chapter has been added to the User Guide. The new chapter provides information that may be helpful while using built-in Active-HDL wizards.
The Value Change Dump (VCD) File section of the Verilog Reference Guide has been updated and supplemented with the information concerning extended VCD files. (SPT65461)
The xnf2edf.exe program (previously used in conversion of XNF files to EDIF netlists) stored in the $aldec\bin directory is no longer installed with Active-HDL.
Appearance of the Getting Started window on Active-HDL startup can be controlled. Displaying the startup screen can be disabled by checking the Do not show this window again option in the Getting Started window. To enable it again, the Show Getting Started window on startup option in the Environment category of the Preferences dialog box should be checked. (SPT65975)
Licensing
An explanatory message related to a license issue is displayed in the Diagnose License dialog box.
Previously, a wrong license type was displayed in the Diagnose program when the floating license was set by using the USE_SERVER entry in the license file. This issue was corrected. (SPT67690)
VHDL Compilation and Simulation
An issue with the resolved
signals of the signed and unsigned
types from the numeric_std package when the
compiler was running in mode compliant with IEEE Std 1076
Previously, using logical operators together with
type casting when the compiler was running in mode compliant with IEEE
Std 1076
An issue with an overloaded function declared in a protected type was revised. (SPT65285)
An issue which occurred when a function returning a vector type was assigned to an aggregate of scalar values was resolved. (SPT67173)
Previously, an error with incompatible ranges was reported when the order of ports in the component declaration was not the same as in the entity declaration when a generate statement and unit configuration were used. This issue was resolved. (SPT65615)
Previously, an incorrect error message was printed to the Console when the size of array was exceeded. This issue was revised. (SPT65568)
An issue with the 'DELAYED attribute applied on a composite type of a port if the port was transmitted to more than one port assignment was resolved. (SPT67232)
An issue with an attribute applied to an access type of an incomplete type causing an improper compilation error was corrected. (SPT66145)
An issue with an external name used as a parameter of a procedure which requires a variable object was resolved. (SPT68065)
Previously, an expression using a constant initialized by a predefined function from the packages of the IEEE library was not recognized as locally static in some cases. The issue was resolved. (SPT66036)
Previously, a concatenation with a slice operand was not connected to a signal which resulted in incorrect simulation results. This issue was corrected. (SPT67929)
An issue with incorrectly calculated value of a constant was resolved. (SPT65667)
An issue with compiling partially encrypted VHDL constructs was resolved. (SPT68493)
The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT64971, SPT64986, SPT65303, SPT65447, SPT65662, SPT65819, SPT66737, SPT67164, SPT67250, SPT67218, SPT67528, SPT67772, SPT67937.
Verilog/SystemVerilog Compilation and Simulation
Using the coverage write command with the -src argument when the source files were missing now triggers a warning instead of an error.
An issue which might cause an infinite simulation loop in certain SystemVerilog designs was corrected. (SPT64616, SPT64948)
Previously, if a single underscore character was the first one read by the $fscanf function, a random value was inserted. This issue was corrected. (SPT66591)
An issue with the $write task that caused incorrect simulation results when stepping through source code was resolved. (SPT68549)
An issue with the sign extension of a signed logical and arithmetic shift left operator used in an unsigned expression was corrected. (SPT64988)
A compilation issue connected with automatic variables in an intra-assignment delay control of a non-blocking assignment was corrected. (SPT68141)
A compilation issue which occurred when more than one encrypted code snippet was placed in a source file was corrected. (SPT64928)
Previously, an incorrect error appeared during incremental compilation when an array of an instance was instantiated. The issue was resolved. (SPT66266)
An issue was revised that caused that the status of Verilog source files added to a design as links did not change after compilation. (SPT65923)
An issue with selecting a correct resolution function when dissimilar net types were connected to a port was revised. (SPT65232)
An issue with input ports connected to a concatenation of a constant and signal which could cause incorrect results when the simulator was running in the SLP mode was resolved. (SPT67281)
The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT64874, SPT65320, SPT65811.
Mixed-language Simulation
If a Verilog module was instantiated in VHDL but its output ports were not mapped, it caused improper elaboration error. The issue was fixed. (SPT65719)
Input ports of the reg type are supported in the Verilog modules instantiated in VHDL. (SPT65754)
The following defects resulting in occurrence of simulator errors were fixed: SPT64829, SPT66007, SPT67102.
PSL Assertion Verification
An issue which occurred during mixed VHDL-PSL
compilation when the compiler was running in mode compliant with IEEE
Std 1076
Previously, a syntax error was displayed when
certain complex VHDL expressions were transmitted to assertions, when
the compiler was running in mode compliant with IEEE Std 1076
Assertion Viewer
An issue with displaying values in the Covered Vacuously and Covered Nonvacuously columns was corrected. (SPT65359)
Libraries
The default value of the SIM_DEVICE generic was corrected in the BUFR component for the Xilinx VIRTEX-4 to VIRTEX-7 libraries. (SPT67155)
Debugging
Initializing the simulation in a design containing breakpoints could lead to unstable program behavior. This issue was resolved.
Design Coverage
An issue which prevented 3 or more databases from being merged was resolved. (SPT66088)
An issue with a signal causing an error after it was added to Toggle Coverage was resolved.
Previously, merging statistics for VHDL design units of the same name but written with a different case triggered an error message. The issue was revised. (SPT65458)
Design Flow Manager
Mouse strokes were disabled in dialog boxes. Previously, performing mouse strokes in the Synthesis Options or Implementation Options dialog boxes could prevent Active-HDL from working.
An issue with the Block Mode option that caused errors in the Actel/Microsemi Designer 9.x/10.x flowcharts was fixed. (SPT66576, SPT67080)
An issue with the use of Microsemi families in the Mentor Graphics Precision RTL Synthesis tool was resolved. (SPT66171)
A defect in the Lattice flowchart causing an error while running the Lattice synthesis tool when a design was stored on a path containing a special character was revised. (SPT66181)
Issues with starting 64-bit versions of the Synplify and Diamond tools from the Design Flow Manager were corrected. (SPT65183, SPT67526)
Previously, the hierarchical RTL-level viewer might not start in version E-2011.03 (or newer) of the Synplify flowcharts. The issue was revised.
An issue with a path to Synplify SDC file was resolved. The absolute path was replaced by the relative one. (SPT65505)
An issue in the Synopsys Synplify flowchart was resolved. It caused synthesis failure due to incorrect paths to SDC constraint files specified in the command.prj file. (SPT66263)
An issue with passing the customized -sd parameter by using the NGDBuild options field in the SmartXplorer Options dialog box was revised. (SPT66934)
An issue with the acom command invoked with an incorrect argument from the Functional Simulation Options dialog box was resolved. (SPT66079)
The following defects resulting in occurrence of an application error were fixed: SPT65105.
Design Browser
An issue with the incorrect compilation status icons displayed for the compiled Verilog files was resolved. (SPT62337)
Design Management
An issue with adding an existing file to a design if the file is saved as a new file with the Automatically add new files to design option selected in the Save As dialog box was resolved. Previously, the file was not attached to the design.
An issue with the library files, created in the $dsn subfolders, which were not visible in the Add to Source Control dialog box was corrected.
An issue with the include directories specified in the Design Settings dialog box which were improperly passed to the compiler was resolved. The issue occurred if the include directories were outside the design directory. (SPT65830)
An issue with changing the hierarchy separator in the Simulation category of the Preferences dialog box was corrected. Previously the change was not remembered. (SPT68501)
Block Diagram Editor
An issue was fixed that caused the following error
was reported while opening a block diagram document (*.bde) created in
a previous version of Active-HDL:
Error: Can't call method "GetLibraryName"
without a package or object reference at <install_dic>Perl\Lib\Aldec\NetlistCreator.pm
line 1752.
In order to fix the issue, it is required to open the block diagram
document and save it to the current file format. (SPT50293, SPT60892,
SPT61176, SPT67072, SPT67228)
Previously, editing a fub if EDIF was set as the target HDL might cause an application error. The issue was corrected.
In the previous version, conversion of a fub to a symbol might cause an application error if an implementation of the converted fub was another block diagram unit and the optimization level was set to -O3.
An issue with the pin names that were not visible when opening a block diagram file was corrected. (SPT68507)
An issue with converting pin names of symbols when the target language was changed from EDIF to VHDL or to Verilog was corrected. (SPT67278)
Previously, editing and saving a symbol shape in the Symbol Editor changed the status of open block diagram documents even if they did not contain the edited symbol. The issue was resolved.
An issue with importing the Viewlogic project using symbols from the Xilinx VIRTEX-II library was resolved. Previously, the symbols were not visible on the diagram document. (SPT67594)
Previously, a bus tap was not created when a bus was connected to a wire. The issue was corrected.
Previously, generating code from the block diagram file containing a specific bus loop could result in creating an empty HDL file. This issue was corrected. (SPT67447)
Previously, generating code from a block diagram file which used the Xilinx UNISIM library with the VHDL VITAL packages could lead to a synthesis error. Excluding these packages from synthesis when the Xilinx UNISIM library was used resolved the issue. (SPT66330)
An issue with using vendor libraries containing units without symbols was resolved.
The Compare Interfaces dialog box was not displayed if a generic of the real type was used. This issue was corrected. (SPT61200)
Issues with displaying generics in the Compare Interfaces dialog box were revised. (SPT67258, SPT67768)
Local generics of a given instance are removed when opening a block diagram file (*.bde). The changes will take effect when the file is saved. Previously, when opening an older block diagram file, the local generics could have the same name which could cause a compilation error. (SPT67358)
An issue with the Compare Symbol with Contents option that incorrectly compared generics between a symbol and its implementation defined in a state diagram was revised. (SPT62640)
An issue related to identical names of generic blocks was resolved by incrementing the name of a block if the given name was already used. (SPT66510, SPT66530)
An issue with a wrong name of a port created by connecting a terminal to a fub was resolved. (SPT61859)
An issue with generics of the integer type with defined range which were not visible in the Compare Interfaces dialog box was resolved. (SPT65473)
An issue with the Compare Interfaces dialog box which incorrectly displayed differences about index range for the std_logic_vector type was resolved. (SPT65465)
Previously, changing the name of a duplicated net to the one that already existed in a block diagram file resulted in modifying all net names with the duplicated name. This issue was corrected. (SPT68530)
An issue with replacing the name of a net was resolved. Previously, connecting a net from a pin component to another net automatically assigned a new name which could not be changed. (SPT50848)
Several issues causing that block diagrams (*.bde) saved to the previous file formats could not be loaded in the current version of Active-HDL were resolved. (SPT66501, SPT66950, SPT67055, SPT67082)
An issue with loading the block diagram files which could lead to an error was resolved. (SPT66239, SPT67229)
Previously, the block diagram document (*.bde) was corrupted when two nets contained the same name. This issue was corrected. (SPT68582)
Previously, incorrect initial values were generated when a conversion function was used. This issue was resolved. (SPT66972)
Previously, port mappings were removed when the symbol was duplicated or copied. This issue was corrected. (SPT65337)
The following defects resulting in occurrence of an application error were fixed: SPT50755.
State Diagram Editor
Currently, the delay counter is added as a signal of the registered type when the delay object is inserted. Previously, it was added as a signal of the combinatorial type. (SPT67888)
Standard Waveform Viewer/Editor
An issue that caused that simulation results could not be displayed when a simulation session was terminated by using the End Simulation button was revised. (SPT66888)
Accelerated Waveform Viewer
Previously, the viewer did not display simulation results after simulation was paused until the waveform was refreshed (e.g. zoomed in or out, scrolled, etc.). The issue was revised. (SPT66166, SPT66251)
An issue with scrolling the Accelerated Waveform Viewer window to the top of the list after adding a new signal was fixed. (SPT64292, SPT65913)
An issue with exporting waveforms to PDF in the Japanese edition of Windows 7 with Service Pack 1 was resolved. Previously, the exported waveforms were displayed incorrectly. (SPT64910)
An issue connected with the Save button on the toolbar of the Accelerated Waveform Viewer window was revised. (SPT62146)
An issue with drawing changes for vectors at a specific zoom range was resolved.
Previously, a blank button was created when the Save to Macro command was placed on the toolbar from the Customize dialog box. This issue was resolved. (SPT67301, SPT66828)
Previously, signal comments were not properly inserted when restoring a waveform from a macro file. The issue was revised. (SPT66803)
An issue with displaying signals in the waveform window was corrected. Previously, the signals could not be displayed when scrolling the undocked waveform window. (SPT67521)
Previously, measurements were removed when the simulation was restarted. This issue was resolved.
Previously, a waveform document was scrolled to the top of the screen after restarting the simulation when at least one of the simulated units was previously recompiled. This issue was corrected. (SPT62526)
Previously, the analog shape of a virtual bus was not preserved when the simulation was restarted. This issue was revised. (SPT67246)
Scripts
The -f argument of the asim command is supported in the VSimSA mode.
An issue with the wrong simulation results while using the when command was resolved. (SPT65502)
An issue with the log or trace command in the VSimSA mode when tracing a slice of a signal was resolved. Since this version of Active-HDL, the whole signal is traced. (SPT65674)
Previously, adding signals with VHDL extended identifiers to a virtual bus by issuing the add wave command containing wildcard characters could cause problems. This issue was resolved. (SPT67675)
A performance issue related to loading the contents of memories by using the -change argument of the mem command was resolved. (SPT66080)
IP Protection
An issue connected with the VHDL `protect key_block pragma was corrected. Previously, the file would not compile if the pragma had more than 80 characters in a single line. (SPT66459)
Active-HDL Interfaces and Wizards
Several issues with model generation that might occur in versions 11.2-14.2 of Xilinx System Generator were resolved in the MATLAB/Simulink interface.
An issue in the Code2Graphics converter connected with generating a state diagram document from an HDL file located in the \compile folder was revised. (SPT66702)
An issue with the font type used in HDL files exported to PDF was corrected. Previously, the default font was used. (SPT65164)
Documentation
Double-clicking some links in the main documentation window caused a script error. The issue was revised. (SPT68106)
Others
In the previous version, the simulation time was not updated or displayed while the simulation was running. The issue was revised. (SPT66167, SPT66198, SPT66228, SPT66277, SPT66343)
For more information about features and changes introduced to previous releases of Active-HDL, refer to the Active-HDL release history. See Help and Documentation Files for details.
The Student Edition of Active-HDL 9.3 is delivered with the following limitations and changes:
Network installation is not available
Number of designs in a workspace is restricted to 1 design
Simulation performance is limited and runs at reduced speed. Limitation on maximum allowed instance is 2000. Simulation will be stopped after reaching this limitation.
Standard Waveform Viewer is not available
Off-line simulation (Post Simulation Debug) is disabled
Simulation of EDIF netlists is disabled
Batch mode (VSimSA) is not available
Block Diagram Editor can contain up to 30 symbols/fubs
State Diagram Editor can contain up to 20 states
Specification of custom stimuli saved in ASDB or VCD files is disabled
Import of all third-party projects is disabled
The export of a workspace/design to HTML/PDF allows exporting block and state diagrams that contain up to 30 symbols/fubs and 20 states. The export of images to vector graphics is unavailable
The team design management is available neither in the GUI nor the command-line mode
Xilinx schematic libraries are unavailable
Additionally, the following options and tools are not available or limited:
Advanced Dataflow Viewer
Advanced PDF Export
Conversion and replacement of block diagram symbols
C Code Debug
Statement/Branch Coverage, Expression Coverage, Path Coverage, and Toggle Coverage
Design Profiler
Follow Object
HDE Actions Recorder/Player
Memory Viewer
Multi-process code generation for state machines
VHPI/PLI/VPI/DPI-C Wizard
Server Farm Integration
Third-party interfaces:
- Spec-TRACER Interface
- Source Revision Control Interface
VHDL Signal Agent
XTrace
Conversion tools for the Standard and Accelerated Waveform Viewer
Design Flow Manager supports only the following
tools:
HDL Synthesis
1. Altera Quartus II 12.1/13.0/13.1 Synthesis & Implementation
2. Lattice Diamond LSE 2.0/2.1/2.2
3. Lattice Synthesis & Implementation in Diamond 2.0/2.1/2.2
4. Mentor Graphics Precision RTL 2009/2010/2011 Synthesis
5. Mentor Graphics LeonardoSpectrum 2008/2009/2010
6. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design
Planner F-2012.03, G-2012.09, H-2013.03
7. Synopsys Synplify Pro F-2011.09/2012.03, G-2012.09, H-2013.03 for
Actel/Microsemi
8. Synopsys Synplify Pro E-2010.09/2011.03, F-2011.09/2012.03, G-2012.09
for Lattice
9. Xilinx ISE/WebPack 14.5/14.6/14.7 XST VHDL/Verilog
10. Xilinx ISE/WebPack 14.5/14.6/14.7 Synthesis & Implementation
11. Xilinx Vivado 2013.1/2013.2/2013.3 Synthesis
12. Xilinx Vivado 2013.1/2013.2/2013.3 Synthesis & Implementation
Physical Synthesis
1. Xilinx PlanAhead 14.4/14.5/14.6/14.7
Implementation
1. Actel/Microsemi Designer 10.0/10.1, 11.0/11.1
2. Altera Quartus II 12.1/13.0/13.1
3. Lattice Classic (supports ispLEVER Classic 1.7)
4. Lattice Diamond 2.0/2.1/2.2
5. QuickWorks 2008.x/2009.x/2010 Implementation
6. Xilinx ISE/WebPack 14.5/14.6/14.7
7. Xilinx Vivado 2013.1/2013.2/2013.3