Software and Hardware Requirements

Active-HDL 9.3 requires:

• A PC with an x86 or x86_64 CPU supporting Streaming SIMD Extensions 3 (SSE3/PNI)

• 256MB of physical memory (512MB recommended, see also the notes below)

• Monitor resolution: 1280 x 1024 (recommended)

• Microsoft® Windows® XP with Service Pack 1 or higher, Windows XP Professional x64 Edition, Windows Server® 2003 with Service Pack 1 or Windows Server® 2008, Windows Vista™, Windows Vista™ x64 Edition, Windows 7, Windows 7 x64 Edition, Windows 8, or Windows 8 x64 Edition

• Microsoft Internet Explorer 8 or higher (see notes)

• Hard disk drive with at least 770MB of free space for minimal installation including only standard VHDL and Verilog libraries (3.52GB for full installation including the Active-CAD Import feature, SystemC libraries, all available system/vendor libraries, and sample designs)

Installing Active-HDL

First Time Installation

To install Active-HDL, insert the Active-HDL installation DVD into your DVD-ROM drive. Active-HDL uses an auto-run feature that will automatically invoke the startup menu, which provides several options. Select the Install Active-HDL option to invoke the installation program.

Then, follow the instructions of the setup wizard.

NOTE: If the auto-run feature is not used, run the setup.exe program from the Active-HDL DVD-ROM to start the installation process.

The following files are copied to the \SYSTEM32 subfolder:

• atl71.dll

• atl90.dll

• inetwh32.dll

• mfc30.dll

• mfc71.dll

• mfc90.dll

• mfc90u.dll

• mfcm90.dll

• mfcm90u.dll

• mfcd30.dll

• mfcn30.dll

• mfco30.dll

• mfcuia32.dll

• Microsoft.VC90.CRT.manifest

• msvcm90.dll

• msvcp50.dll

• msvcp70.dll

• msvcp71.dll

• msvcp90.dll

• msvcr70.dll

• msvcr71.dll

• msvcr90.dll

Selection of Optional Components and System Libraries

The installation program of Active-HDL allows you to select components that will be copied or set up during the installation. You can also choose whether to install VHDL, Verilog or both VHDL and Verilog libraries. The selection results in the installation of different system and vendor libraries that are copied during the installation. The optional components and libraries can be selected in the Active-HDL Setup Program - Setup Type dialog box. This dialog box provides the following options:

• Active-CAD Import
  When this option is enabled, you can install Active-CAD executables and auxiliary files necessary to import Active-CAD designs to the Active-HDL environment. The Active-CAD files are copied to the \Active subfolder of the installation directory if Active-HDL is installed on 32-bit versions of Windows. Since Active-CAD is not supported on 64-bit platforms, no files are installed even if this option is checked. If the option is not selected, the \Active subfolder is not created during the installation.

• Network Setup Installation
  This option adds an additional component that can be used to start and use Active-HDL from a remote computer (client). When the installation of Active-HDL is finished (on a server), the \NetSetup directory contains the setup program that can be run from a client computer and install on this computer the Active-HDL Network Client software. The installation of the Active-HDL Network Client contains only configuration files and files that are necessary to establish communication between the client machine and the workstation where Active-HDL is installed. Refer to Network Client Installation for additional information.

• SystemC Libraries
  If this check box is selected, the installation program will install SystemC Class Library files. The files are copied to the \SystemC subfolder of the Active-HDL installation directory. If this feature is not selected, the subfolder is not created during the installation.

• Run MATLAB/Simulink Interface Setup
  This option allows automatic installation and setup of the Active-HDL Co-simulation Interface to Simulink directly in the MATLAB environment. (The interface is required to start Active-HDL-Simulink co-simulation. Prior to running the Active-HDL installation, the MATLAB software must be installed first.)
  The configuration process of the co-simulation interface is started during the Active-HDL installation. In the Simulink Interface Setup dialog box, you will be asked to enter the path to the $matlabroot\bin\win32\matlab.exe file. Clicking on the Next button adds the Active-HDL Toolbox block to the Simulink Library Browser and installs the help documentation in the MATLAB help system. If this option is disabled, you will still be able to setup the interface in MATLAB after the process of the Active-HDL installation is finished.
  The interface files are stored in the \Simulink subfolder of the Active-HDL installation directory regardless of whether the Run MATLAB/Simulink Interface Setup option is checked or not during the Active-HDL installation.

• Vendor HDL Libraries
  Checking this option allows you to select in the subsequent dialog box which VHDL and/or Verilog simulation/schematic libraries will be copied during the installation of Active-HDL.

Regardless of the selected set of simulation libraries, the functionality and supported features depend ultimately on the purchased license only. Active-HDL 9.3 delivers the updated help information that is not limited and it provides the help system for all implemented options and new features.

Manual Installation of Vendor Libraries

The installation program of Active-HDL provides additional programs that allow users to (re)install individual vendor-specific libraries after the installation of Active-HDL. The libraries are stored in the \Verilog and \VHDL subfolders (\Install). The \Sch subfolder contains the installation program of the Xilinx Schematic Libraries. To install a library, start the setup.exe program in an appropriate language and vendor subfolder and follow the on-screen instructions.

Re-installation

The installation program of Active-HDL does not detect whether it has been already installed or not and it does not provide the Add-Remove option. To add or remove some Active-HDL components, you must completely re-install the software.

Installing Updates and Service Packs

Updates and Service Packs for Active-HDL fix problems found in the latest release, provide new features and enhancements that increase design evaluation and simulation performance, and update both the system (ALDEC, IEEE, STD, VITAL2000, VL, EXEMPLAR, SYNOPSYS, SYNPLIFY) and Vendor-Specific Libraries. The remaining libraries (user-defined) need to be re-compiled after the installation of Service Pack.

The installation program will install only the pre-compiled system libraries if you start Update or Service Pack that has been downloaded from the Aldec Update Center home page. In this case, the simulation libraries for synthesis and/or implementation tools also need to be downloaded and updated individually.

If you run an Active-HDL update build from the Service Pack DVD (\Install\Setup.exe), both the system and vendor libraries will be updated.

Previous Version Installed

Active-HDL 9.3 allows installing the previous versions of the software. Each version can be run independently and stored in a separate folder on a disk. Prior to running a newer version of the software, you must update your license as licensing for version 9.3 has been changed and differs from previous editions of Active-HDL.

Directory Structure

By default, Active-HDL is installed in the C:\Aldec\Active-HDL <version> folder. The structure of the folder is discussed in Table 1.

Table 1

Extensions for Active-HDL files:

Table 2

Network Client Installation

Active-HDL 9.3 supports network client installation. In the client-server configuration, Active-HDL is installed on a network server and network users run the program directly from the server. Each user must have the Active-HDL Network Client installed locally on the computer. The Active-HDL Network Client Setup copies the minimum set of files required locally on the user's computer and remotely registers the files from the server. The performance of Active-HDL clients depends strictly on the network performance as well as the number of clients running at the same time. The Active-HDL copy installed on the server must have a network license for the appropriate number of users.

The procedure for installing Active-HDL on a network server is the same as installing a regular version on a workstation. The only limitation is that the path to the installation folder on the server cannot contain spaces. Once Active-HDL has been installed on a server, the client versions can be installed on workstations.

The procedure of installing the Active-HDL Network Client is as follows:

1. Check whether the folder, where the Active-HDL Network Server is installed, is visible and shared (in read-only mode) for all users.

2. It is recommended to map the directory (a parent directory of the Active-HDL installation folder; by default, the \Aldec directory is set) or the server drive on which Active-HDL has been installed. It is very important that you do not remove or modify this mapping because Active-HDL files residing on the server are registered remotely on each user computer. Any change to the mapped network drive will make the client installation unusable.

3. Using the Windows Explorer, find the \Netsetup directory in the Active-HDL Network Server installation folder. The \Netsetup folder contains the setup.exe file. Run this file.

4. Follow the instructions of the Active-HDL Network Client Setup Wizard.

Licensing

The detailed information about Active-HDL licensing can be found in the License Information Guide. To open the guide, double-click the LicenseNotes.chm file stored in the \Books subfolder.

Known Problems

Licensing

• The error message, for example: There was a problem sending the command to the program, is displayed while opening the .aws or .adf file from Windows. To turn off the error message, clear the Show License Configuration dialog box on Active-HDL startup check box in the Diagnose License dialog box (Help | License Information) and click the Apply button. (SPT63701)

Compiler

• Alias declarations occurring in packages may cause an internal compiler error or prevent the initialization of simulation.

• The STD.FOREIGN attribute attached to subprograms is ignored.

• Extended identifiers used as library names are incorrectly interpreted.

• Problems exist with deferred constants, which are defined (in the package body) by an expression containing other constants defined in the same package body.

Example:

package p is

  constant c: integer; -- deferred constant

end;

package body p is

  constant c1: integer := 0;

  constant c: integer := c1; -- this statement may cause application error

end;

Work around (optional solutions):

1. Define the constant value immediately in the package:

constant c: integer := 0;

2. Use the following declaration in the package body:

constant c: integer := 0;

• The gcc and Microsoft Visual C++ compilers delivered with Active-HDL generate different code for shift operators. This may result in different behavior of applications when arguments are shifted for more than 64 bits. (KRK49)

• Compilation may fail or source files may be compiled incorrectly if they are located on paths specified with the use of the double-byte character sets (DBCS), e.g. the Japanese or Chinese character sets (that cannot be represented in a single byte). (SPT47451)

Simulator

General

• During the initialization of a design employing VITAL models, the negative constraint calculation phase is launched only if SDF files are loaded. This phase should be launched irrespective of the availability of the SDF files.

• Internal memory fragmentation leading to increased memory allocation may occur if simulation is restarted several times. (DKO2370)

• If VSimSA is interrupted by closing the system console window while simulation is running, the wave.asdb.error file, and wave.asdbw folder along with its contents remain on disk. These are temporary items, and if needed, they can be safely removed by the user. Furthermore, they do not impede subsequent simulation sessions, and are automatically removed when new simulation is run.
  Regardless of the above, it is recommended to end simulation by issuing the endsim command. (MRP3553)

Verilog Simulation

• The automatic detection of top-level Verilog modules works correctly only if you compile all files into the empty design library. The top-level detection does not work for Verilog files compiled separately.

• It is not possible to stop logging signals to a waveform file. Once a signal is added to a waveform file during simulation (with the trace or add wave command), it will have its complete history till the end of simulation.

• The $force task with the specification of the Random stimulator does not work (JKL59).

SystemVerilog Simulation

• Regular arrays cannot be assigned to dynamic arrays and vice versa.

• Assignments using literals are not supported.

• C-like operators (+=, ++, --, etc) cannot manipulate queue/array elements.

• The $ sign cannot be used to refer to the last element of the queue. (It can only be used when declaring the queue.)

• The foreach loop cannot be used to iterate over array/queue elements.

• System functions, e.g. $size are not available for arrays or queues.

• Fields of classes and structures cannot be accessed by appending the dot and the field name to the indexed name (i.e. an array/queue element).

• A data container cannot be placed inside a structure or a class.

• Regular arrays of dynamic arrays, associative arrays, and queues are not available.

• Several object types, such as unpacked structures or strings cannot be placed inside arrays and queues.

• Data containers cannot be passed by reference

List Viewer

• You cannot load previously saved files into the List Viewer window if they contain:
  1. Simulation results for objects of physical types.
  2. Extended identifiers.

• An application error occurs after the endsim command terminating a simulation session with an ASDB database enabled if the Standard List Viewer containing simulation results of the previous simulation session is still loaded. (JKL995)

• Elements of Verilog registers that were optimized by the compiler cannot be observed correctly in the list window during the simulation and may cause application error. (WOW241)

Design Flow Manager

• Project load time increases if the Design Flow Manager is enabled.

• The following problems may occur while using the XILINX ISE, Foundation, Alliance, WebPack 4.1 Flow:

1. Auto-Devices for packages (e.g. CP, PC, FT, etc.) are not supported
2. Synthesis with the use of Synopsys FPGA Express v. 3.6:
  - speed grades for some XILINX COOLRUNNER devices are different
3. Synthesis with the use of Synplicity Synplify v. 7.0:
  - the following devices of the SPARTANXL family are not supported: XCS30XLCS280, XCS40XLCS280
  - there are differences in references to VIRTEX2P (VP20, VP50) devices in ISE and Synplify
  - speed grades for some XILINX XC9500XV devices are different

• The following problems may occur while using the Xilinx WebPack 3.3 Flow:

1. Synthesis with the use of Synopsys FPGA Express v. 3.6:
  - speed grades for some XILINX XC9500XV devices are different

• The following problems may occur while using the Xilinx Foundation, Alliance 3.3 Flow:

1. Synthesis with the use of Synopsys FPGA Express v. 3.6:
  - devices of the XC3000xx and XC5200 family are not supported by this version of the program
  - some devices of the XC4000XL and XC9500XV family are not supported by this version of the program
2. Synthesis with the use of Synplicity Synplify v. 7.0:
  - some devices of the XC4000XL and XC9500XV family are not supported by this version of the program
3. Synthesis with the use of Exemplar Leonardo v. 2001.1d:
  - devices of the XC3000xx and XC5200 family are not supported by this version of the program

• The Use Server Farm list boxes in the Flow Configuration Settings dialog box do not remember names of farm controllers that previously have been connected by using the Active-HDL Farm Manager. (RYB1425)

• For the Exemplar Flow for Chip Express and Synopsys FPGA Express (Xilinx OEM) flowcharts, the Flow Configuration Settings dialog box displays the full list of device families, instead of device families that are currently supported by each of these tools. (MIP2687)

• The Refresh file list button does not work if the Run implementation with selected command file option has been selected. (ROD61)

Block Diagram Editor

• Block diagrams are incorrectly reproduced in PDF files obtained from printing with the Acrobat PDFWriter driver.

• Problems exist with editing symbols from system libraries.

• The Check Diagram option incorrectly reports errors if VHDL entities containing extended notations are instantiated on Verilog block diagrams.

• The HTML links from DRC reports do not work when the Netscape Internet Browser is used.

• The Paste operation of block diagram contents to Word 2000 works incorrectly. The Paste Special option must be used instead of this.

• The Show in Generated Code (F3) option may not work in original designs created in previous versions of Active-HDL. To use this option in the Block Diagram Editor, you need to (re)generate the HDL code.

• The Show in Generated Code (F3) option is available only on one page of the multi-page block diagram (the one from which a code has been generated).

• The Find option of the HDL Editor built-in the Block or State Diagram Editor (standalone HDL Editor window) is limited and works only for the Direction-Down setting.

• The shape of a symbol on a block diagram is not updated after it has been updated in the project's local library. (ARG362)

• The HDL code patterns generated for the m2_1 (2-to-1 Multiplexer), m2_1b1(2-to1 Multiplexer with D0 inverted), and m2_1b2 (2-to1 Multiplexer with D0 and D1 Inverted) symbols, located in the Build-in symbols library, have been changed to be compatible with the XC4000E library. (ZBR2)

• Enabling an automatic insertion of conversion functions reloads a block diagram, which deletes the Undo/Redo history. (ANK1069)

• Asian fonts (double-byte characters) may be displayed incorrectly on block diagrams if they are used as identifiers. The characters used in comments are displayed properly. (ANK1105)

• The Generate structure and Autoformat text options are disabled in text documents opened by using the Edit Using HDE option available in the context menu of the text blocks (HDL statement, declaration, header blocks, etc.).

Code2Graphics Converter

• If both VHDL and Verilog source files are converted to state diagrams, the HDL code of all target FSM documents is of the language of the first source code file to be converted.

• The Code2Graphics Converter does not support Reset of the Boolean type.

• The Code2Graphics Converter does not support asynchronous machines.

• The Code2Graphics Converter does not support synthesis attributes for Verilog HDL. (ARG440)

• The compound buses are not supported if they consist of scalars and vectors. (MIP2563)

• The constrained compound buses are not supported.

State Diagram Editor

• If a concatenation operator is used on the left side of action then correct values may be assigned to concatenated elements under the following conditions:

1. The right side of an assignment is a constant number.

2. The operands with bit-select or part-select of vectors are not used (only the entire vectors may appear as concatenated elements).

• The signals and ports of the vector type may get an incorrect initial value if the default value is not explicitly defined for such objects and there is no assignment to the entire object in the reset state.

• The inout ports in Verilog may be used as inputs only. An attempt to assign a value to an inout port will cause a warning and action will be ignored.

• The Find option of the HDL Editor built-in the Block or State Diagram Editor (standalone HDL Editor window) is limited and works only for the Direction-Down setting.

• When the following conditions are met during the code generation:

1. A combinatorial port in the state entry action is used

2. There is a transition to this state with a condition using a variable

3. This variable has been declared within the FSM frame

then the generation process is stopped and an appropriate error is reported in the Console window.

• Users who migrate their projects from an older version of Active-HDL may encounter the following error reported by the VHDL code generator:

Example:

# Error: COMP96_0015: BACKREQ.asf(BACKREQ.vhd) : (57, 12): '<=' expected

This version of the State Diagram Editor (code generator) requires a valid assignment operator (<=) in state actions.

• It is recommended to use the One Process style of the VHDL code generation in case a variable is used in the state machine project. In projects employing the Two/Three Processes code generation style, operations on variables will not be performed correctly since they are declared in processes that do not have Clock on their sensitivity list.

• The Enable Verilog Parser option disables the Add missing semicolons option while generating the Verilog code.

• The Testbench Generation option does not support the following features:

1. An incorrect testbench may be generated in case a state machine employs bi-directional ports. If the bi-directional ports are only read or updated, the testbench will be generated correctly.
2. An incorrect testbench may be generated in case an inout port is of a different type than STD_LOGIC in VHDL and Logic in Verilog.
3. This option does not support process/always statements in Diagram Actions and case in other Actions.
4. Only '1' and '0' are supported for STD_LOGIC, STD_ULOGIC, and Logic.
5. This option does not support the concurrent state machine projects (if several machines are specified in one diagram and there are some operations on signals in one machine and other machines use the results of these operations, e.g. a signal from one machine is used in the transition condition of another machine).
6. This option supports standard libraries only. It does not support user-defined libraries and packages.
7. The vectors of the width up-to 64 bits are supported. An incorrect testbench may be generated in case other vectors are used.
8. This option does not support time delays.
9. This option does not support user-defined types of ports.
10. An incorrect testbench may be generated in case a signal has been declared in the Diagram Declaration and Diagram Action.
11. Strategy 3 is not available for asynchronous machines.
12. For signals and variables without default values '0' is set.
13. If there are transitions coming out of a state and they have conditions that complement each other, the following warning will be generated during the testbench generation:

  Cannot go through transition

Clicking this warning you can see the state for which the @else transition has not been checked. In this case the test quality for transitions does not equal 100% although the Code Coverage Viewer reports the 100% coverage.
14. The above mentioned warning is generated at the specified time. It does not mean that the testbench generator is unable to go through the selected transition at all.
15. The following warning means that the testbench generator did not go through a given transition:

  Transition is absent in the generated testbench

16. An incorrect testbench may be generated in case the IF statement is used in the State Action, and there is an operation on a variable inside this statement (IF) and this variable is used in the condition of the transition leading to another state. During simulation, the Waveform Viewer will display the transition from a given state (with the IF statement in the State Action) with the one-clock-cycle delay. In such cases the use of signals is recommended instead of variables.
17. An incorrect testbench may be generated in case Action contains operations on a signal (addition, subtraction, etc.) and in Transition a value of the lower or upper range of this signal is used. While going through this transition the value of this signal will be out of range. If such a problem occurs, it is recommended to increase the range of value for this signal.
18. An incorrect testbench may be generated when some operations on variables are performed within one Action and the result of an operation on one variable is used in an operation on another variable.
19. The testbench generation process may be time consuming or incorrect (incomplete) testbench may be generated in case a machine must stay in a given state performing some operations until the condition is met.

• A text placed on a diagram may be displayed incorrectly after the change of the zoom. (MIP2337)

Waveform Viewer

Standard Waveform Viewer/Editor

• Adding variables from processes to the Standard Waveform Editor window may disable displaying of some signals.
  Workaround (optional solutions): First, add the desired signals, then add the variables.

• In case there is a wave whose Verilog strength does not have the VHDL std_logic mappings assigned (small, medium, weak, large, supply), the Standard Waveform Viewer/Editor does not display this wave in the Waveform Editor window.

• The Compare Waveforms option may work improperly for waveforms coming from previous versions of Active-HDL To avoid this problem, save the waveform document in a new format and then run the Compare Waveforms option.

• The comparison of signals of the real type may work incorrectly. (MIP2455)

• The problems with refresh after a measurement has been deleted may occur. (ZBR1144)

• The Time per Page setting is sometimes calculated incorrectly. (MIP2586)

• Waveforms that contain signals with a large number of transitions are printed in black instead of gray. (JAG9)

• Waveforms produced during very long simulation runs (e.g. exceeding 10000s) may be displayed incorrectly or some of waveforms may be presented incompletely. (ARG2580)

• Arrays of real values, multidimensional arrays, and sparse memories cannot be observed.

• Elements of Verilog registers that were optimized by the compiler cannot be observed correctly in the waveform window during the simulation and may cause application error. (WOW241)

• The Empty Row object cannot be located as the first object in the waveform window. If it is moved to this position, the row is removed from the waveform view. (KAM3920)

Accelerated Waveform Viewer

• The Find option does not work if the width of vectors exceeds 32 bits. (KAM1628)

• Sparse memories cannot be observed.

• The simulation database files (*.asdb) generated in Active-HDL 8.3 (or newer) can be neither opened in the previous versions of Active-HDL nor used during post-simulation debug sessions (PSD mode). An attempt to open the database or initialize post-simulation debug session will cause an error. The following error messages are generated in the Console window:

# Error: Cannot connect to <path to ASDB file> database

or

# Error: The specified file <path to ASDB file> is corrupted or is not supported in the current waveform mode.

The Waveform View Configuration files (*.awc) generated along with the ASDB database in version 8.3 (or newer) can be opened in earlier versions without any error, but no signals will be presented in the Accelerated Waveform Viewer window. (MRP3297)

Simulink® / MATLAB® Interface

• Dynamic sizes of ports are not supported in the HDL Black-Box for System Generator block.

• The force <MAT-file_stimulus> command does not work with 64-bit versions of MATLAB.

SWIFT™ SmartModels Library Interface

• Selected models from the SmartModels library require delay annotation for proper operation. Delays are created with specify blocks in Verilog wrapper files. Such delays are ignored by Active-HDL unless SLP acceleration is enabled. (SPT13304)

• Values of SmartModel windows cannot be set if the model is instantiated in a Verilog design.

Interfaces to Third-Party Tools

• The DPI-C Wizard does not show the names of the generated items after it is closed and re-opened. (KAM3526)

Library Manager

• The Library Manager reports the following error if a global library is loaded as a project and accessed through a double-click method in the Design Browser window:

Error: Library Manager: Library <library_name> not found

• Adding IP Core symbols to the Symbols Toolbox may work incorrectly. (ARG334)

Testbench Generation

• If a waveform contains a signal with the same name as the output port of the unit for which the testbench is generated, then during testbench generation the stimuli will be applied to this output port as well.

• If Verilog testbench generation is based on waveforms created for the VHDL unit then VHDL signal values are not converted into the allowed Verilog signals.

• If the testbench generation is stopped by using the Break button from the main menu the following error may be reported:

# Error: ^C at <active-hdl_installation_path>\Perl\Lib/Aldec/ffc.pm line 65.

Active-HDL and VSimSA Scripts Incompatibility

• The macro commands used in Active-HDL are not case sensitive, whereas VSimSA requires the macro commands to be written in lowercase.

HDL Editor

• The HDL Editor can show the Verilog code as a comment if commentary signs are present in the escape identifier.

• The Find option of the HDL Editor built-in the Block or State Diagram Editor (standalone HDL Editor window) is limited and works only for the Direction-Down setting.

• The Auto Complete option may complete keywords incorrectly if the upper case is on. (MIP2465)

Design Browser

• The Design Browser may work slowly and does not refresh the contents of the Files tab when a design contains hundreds of files. (JAG42)

• After opening a design from the older version of Active-HDL, the design structure is initially collapsed. This problem occurs only if the design is opened for the first time in the newer version of Active-HDL. (MAN2327)

• Some files do not open when they are dragged from the non-active design structure in the Design Browser to the document window area. (ZBR1110)

• After a compilation is run from a macro file, the name of the active library is no longer distinguished in bold. (MAN2328)

• If a workspace is loaded and a new library is created, the newly created library project is temporarily displayed in the Files tab. (ELF4014)

• During the compilation of source files that use the same entity name, the entity of subsequent units is skipped, which affects the correct display of the entity/architecture pair compiled as the very last one. (ARB57)

• SystemVerilog packed and unpacked structures cannot be expanded in the Structure tab. (ARG2522)

• SystemC objects of the vector type are presented in the Structure tab as scalars. (REM1859)

• After a simulation session is finished with the endsim command or by using the End Simulation command from the Simulation menu, ports and components instantiated in SystemC modules are not shown in the Structure tab. During simulation, all ports and components are displayed properly. (REM1929)

• Ports and signals of a SystemC module instantiated in another SystemC module are invisible in the Structure tab in the Post-Simulation Debug mode. (REM1872)

• The options for adding objects to Advanced Dataflow and Waveform as well as Toggle Coverage and XTrace operations are not grayed out for encrypted units. Since the contents are hidden, these commands cannot be executed on such component types. (KRS446)

• Displaying very large objects in the Object List Viewer of the Structure tab may cause unstable behavior. (ARG4627)

Export Design to HTML/PDF

• The values of signals stored in the List file (*.lst) are always exported with the binary radix regardless of their actual radix set in the List window. (ELF3932)

• The problems with displaying HTML Projects in the Netscape Navigator 4.7x browser can be encountered. (MIP2766)

• The waveform documents in the HTML Project do not show signal icons. (ZBR1088)

• For some waveform graphics settings (set in the Export to HTML wizard), the grid is not exported to the graphical file even though the appropriate option has been checked in the wizard. (GRJ26)

• Exporting textual source files to HTML from the undocked window minimizes the HDL Editor window. (ELF3863)

• The graphical objects of the Windows Meta File (*.wmf) or Windows Enhanced Meta File (*.emf) format placed on a state diagram cannot be exported to the PDF format file.

• The starting page of the exported PDF documentation is empty if the first exported file is an HTML document. (MRP3136)

• HTML documents containing frames are not exported correctly to PDF. (MRP3145)

Export to Graphics

• After exporting selected signals, the bus signals are not expanded in the generated graphical file even though the Expand buses and Selected signals only check boxes were selected in the Export Waveform to graphics dialog box. (ELF4114)
  
  Workaround:
  Expand the buses that you want to export and select all their component signals before invoking the Export Waveform to graphics dialog box.

Import of Third-party Projects

• The import of Active-CAD project does not work on all Windows x64 platforms.

• The import of Xilinx ISE 12.1 projects does not work. (KAM5067)

C/HDL Debug

HDL Debugger

• The breakpoints set on the EDIF signals do not work.

• The scrolling in the Debug window (e.g. in the Design Browser window) is slow when a wide bus is expanded.

• The Structure tab of the Design Browser window displays unavailable value in the Value column for the Verilog event type.

• The Structure tab of the Design Browser window does not display a value for the bus slice connected to the component's input port.

• The copy of a signal can be added to the Watch window after the design has been reloaded.

• The Last Value column (Design Browser-Structure, Watch) may be unavailable or display incorrect values for Verilog regs, wires, or memories. It is recommended to hide this column while working with Verilog designs.

• If signals are added to a waveform during simulation with the Post Simulation Debug option on, then these signals will be visible in the Standard Waveform Viewer window after the initialization of simulation from the *.psd file.

C Debugger

• The value of expressions using unary operators (the increment operator (++) or the decrement operator (--)) displayed in tooltips and C Code Debug window may be calculated incorrectly. (KAM1126)

• The Call Stack tab in the C Code Debug window may not work properly. (JAK12)

• Debugging C code on Windows Vista x64 Edition is not supported. (JKL1382)

Advanced Dataflow

• The Advanced Dataflow Viewer does not display the $monitor task. (ELF4929)

Memory Viewer

• The background of memory cells does not change if a variable or reg is used to model a memory object. (ANK1198, SPT13795)

• Multiple objects of the same name that differ only in the case of their hierarchical path can be added to the Memory View window. (ANK1291)

• Changing a value of one of record elements overwrites values of remaining elements of this record. (REM616)

Follow Object

• The Follow Object option does not display the $monitor task. (ELF4929)

Console

• The refreshing problems may occur when a large amount of messages is being scrolled in the Console window.

Mixed HDL Designs

• In mixed-HDL designs, port mapping may be done by named association only.

Installation

• The installation program does not detect itself (if Active-HDL was previously installed) and it does not include the Add-Remove or Change options.

• During installation of Active-HDL Network Client from a mapped network drive on Windows 7 machines an incorrect warning may be issued regarding installation from a UNC path. The warning is irrelevant and can be ignored.

Scripts

• The change command requires all parameters to be specified without the space character.
  Example:
  change Q_0_OBUF/tpd_I_O (4ps,4ps)

• If the continue command is the very last command on the command list of the when command, the simulation does not stop. (MRP682)

• The do command does not support the -start and -stop arguments if -tcl or -msim are specified simultaneously in the command line. (JKL1937)

• The enableba macro command does not enable corresponding breakpoint when the -vacuous, -nonvacuous, or -extra arguments are used. (MKZ92)

• The if statement is incorrectly interpreted if the condition operands are double-quoted and there is no white space between the operands and the comparison operator, i.e. "0"="0". (MIP2754).
  Workaround:
  Insert spaces between arguments and the comparison operator or place the entire condition in the curly brackets, i.e. {"0"="0"}.

• The onbreak and onerror commands are not supported in the Tcl and Compatibility Mode. (MIP3630, MRP2866, MRP2867)

• The setactivelib command does not set an active working library correctly if there are several macros executed at the same time that contain this command. (ELF4551)

• The waverestorecursors command does not work properly if the Standard Waveform is set as the default waveform viewer and the number of the <time> parameters specified in the command line is less than the number of the timing cursors inserted to the waveform window. In this case, the cursors for which the <time> parameter was not specified are removed from the waveform window. (KAM3911)

• The write command does not save files to folders defined in the Design Structure category of the Preferences dialog box. By default, the command saves files to the current working directory. (JKL3428)

• Active-HDL does not prevent the pre-defined environment variables from overwriting in the Tcl and Compatibility Mode. (ARG3280)

• Some profiling data may be collected even if an optimization method (-o<n>) has been on. (ARG622)

• If the default Console message prefix (#) is changed to another character or a string, compilation macros generated by the Generate macro utility will contain both commands and messages printed to the Console. (JKL2680)

• Migrating Tcl/Tk scripts from the older versions of Active-HDL (e.g. 7.1 or 7.2) may result in different behavior of user-defined applications while executing scripts employing Tk graphical extensions. This issue occurs due to the upgrade of the Tcl/Tk engine from version 8.0 to 8.4. Previously, execution of the following sample script resulted in opening a Tcl window:

##### start #####
set w .options
toplevel $w
wm geometry $w =300x200
##### end #####

Now, this script will execute and the window will close immediately. In order to fix this issue, modify the script by adding the tkwait command, for example:

##### start #####
set w .options
toplevel $w
wm geometry $w =300x200
tkwait window $w
##### end #####

Note however that the use of the tkwait command disables pre-defined Active-HDL accelerators. (SPT15023)

• The Perl interpreter requires the Microsoft Visual C++ 2008 Redistributable Package (x86) which is not available in Windows XP. It is recommended to install the package to prevent the errors related to the Perl interpreter embedded into Active-HDL from occurring when using this version of Windows. The Microsoft Visual C++ 2008 Redistributable Package (x86) can be downloaded from the Microsoft Download Center. (REM2963)

Framework

• Old display drivers for some graphic adapters working in the True Color mode may incorrectly reproduce colors. As a result, the toolbar icons are displayed as black spots and the problem persists even if you refresh the screen. Solution: install updated display drivers or switch to the 64K or 256 color driver.

• Some options may work incorrectly if the working window is undocked.

• Adding or removing new toolbars in the Customize window may work incorrectly. (MAD857)

Preferences Manager

• The Active-HDL Preferences Manager omits random parts of preferences while exporting/importing them to/from an external file (*.dmp). (ARG295)
  Workaround:
  Before the export of preferences, open the Preferences dialog box (Tools | Preferences), visit every view in this window and then click the OK button.

• The Active-HDL Preferences Manager does not export the current setting of the hierarchy separator (Tools | Preferences | Simulation | Use hierarchy separator) (ARG414).

• The Active-HDL Preferences Manager does not export the current flow setting (Tools | Preferences | Flows | Select Flow). (ARG407)

• The Active-HDL Preferences Manager does not export and import the current toolbar setting (location, icons, etc.). (ARG474)

• The Active-HDL Preferences Manager exports/imports the settings for programs specified in the Tools category of the Preferences window. (ARG789)

Windows XP/Vista/7

• The context help may not work when Active-HDL is installed on a workstation with Windows Vista, Windows 7, or Windows Server 2008. Refer to Product Help for additional information.

• When the User Account Control is enabled (the UAC level is higher than Never notify), dragging and dropping design files onto Active-HDL window from other applications (e.g. Windows Explorer) may be disabled. To restore the drag-and-drop functionality, the UAC must be disabled (set to its lowest level). (SPT51051)

Source Revision Control Interface

• The problems may appear while adding a group of files created automatically to the source control system database.

• The files invisible on the Files tab of the Design Browser window are not added automatically to the source control system database.

• The files for which links are visible in the Design Browser window are not added to the source control system database.

• If a design is added to source revision control database by using the Synchronicity interface, the Design Browser generates superfluous message box saying that design files have been modified outside Active-HDL (ZBR1785).

• The Open Design from Source Control option does not work. When this option is used a design is only copied to the \My_designs subfolder. (ZBR1798)

• The Open Design from Source Control option does not work if Razor or QVCS is set as a Source Revision Control system. (ARG1063, MRP362)

Server Farm

• The Server Farm is not supported on Microsoft Windows Vista platform. (JKL999)

• The Server Farm uses system environment variables instead of the user environment variables. This may cause problems with running tools on server computers that take advantage of the user environment variables to access the license. (ZBR1061)

• The paths to the synthesis and implementation tools provided in the Server Farm Properties dialog box are ignored. Consequently, the farm controller has no access to these tools and cannot run scheduled tasks. (ZBR1036)
  
  Workaround:
  Append the necessary paths to the PATH system variable on a server.

Code Coverage

• The COUNT value displayed for the while and the repeat instruction may be different then in other coverage tools. The COUNT value for the while instruction may be one greater.

• The COUNT value is displayed only for those subprograms that have been used directly during simulation. The subprograms that have not been used during simulation are not counted and are displayed in gray.

• The COUNT value is displayed only for the variable and constant declarations declared within subprogram bodies and having initial values assigned. The COUNT value for the variable and constant declarations declared within processes and having initial values are not displayed.

• The Coverage Report option of the Code Coverage Viewer does not work (a report is not generated) if the path to the folder, where the report file is to be generated, includes the Space character.

Toggle Coverage

• Arrays of real values and multidimensional arrays are ignored by the Toggle Coverage. Toggle Coverage data cannot be collected for such objects.

Programming Language Interface (PLI)

• The header of the aldecpli.h file located in the <install_dir>\PLI\Include subfolder has been changed. Because of this change all user C-projects used in previous versions of Active-HDL PLI-based designs have to be recompiled with the new header.

IP Core Generator

• The bds2lib.exe program does not support spaces in paths in the command syntax. It may cause problems with generating symbols in the IP CORE Generator module. (ARG373)

• The IP Core Generator module uses the Perl interpreter embedded into Active-HDL. There is an issue related to Perl which prevents the interpreter from working properly under Windows XP. For more information, refer to the Scripts section. (REM2963)

Product Help

• Some dialog boxes may display no context help information or it can be displayed incorrectly. (ANK1236)

• The context help (i.e. Help files (*.hlp) created in the Windows Help format) is unavailable when Active-HDL is installed on Windows Vista, Windows 7, or Windows Server 2008. Refer to the technical documentation of the operating system or the KB917607 Microsoft Knowledge Base Article.

• The Search tab does not allow finding help topics for the when macro command. In order to find the information about when, type in "when command" in the Type in the word(s) to search for edit box. (ANK1222)

• A new window of the Product Help may stay in the background if another Active-HDL help window was opened. (WOW1361)

• If more than one instance of Active-HDL is running, then opening the documentation window (Help | Product Help) for the first instance causes that the help documentation of a subsequent instance is started as a minimized window visible in the task bar. (ANK1416)

Others

• The folder 'My Designs' (including the space character) may be the reason of some problems in Synopsys™ and Xilinx™ tools.

• If there are several local libraries attached to a design and corresponding library index files (*.lib) are stored in one directory, then the Save Design Status option prints to the log file incomplete or incorrect information about units compiled to inactive libraries. (ARG3842)

• A large number of opened documents may result in GUI malfunctions (disappearing toolbars etc.). For more information, read the article on Microsoft support page http://support.microsoft.com/kb/126962.(WOW3485)

Unsupported Verilog Constructs

• The defparam keyword is not implemented for arrays of instances.

Unsupported ACC Routines

• acc_append_pulsere

• acc_fetch_pulsere

• acc_handle_interactive_scope

• acc_replace_pulsere

• acc_set_interactive_scope

• acc_set_pulsere

For more information and the complete list of ACC routines, see PLI Reference Guide in the References section.

Unsupported TF Routines

• tf_read_restart

• tf_write_save

For more information and the complete list of TF routines, see PLI Reference Guide in the References section.

Unsupported VHPI Routines

• vhpi_get_data

• vhpi_get_next_time

• vhpi_protected_call

• vhpi_put_data

For more information and the complete list of VHPI routines, see VHPI Reference Guide in the References section.

System Libraries

Standard Libraries

The following is a list of packages for which the Active-HDL simulation kernel provides the built-in acceleration:

Table 3

1) The ALDEC system library contains two source files that are not compiled into the library (aldec_builtins.v and aldec_builtins.vhd). The files contain the functional description of primitives corresponding to the Built-in Symbols available in the Symbols Toolbox of the Block Diagram Editor. The files are required only during the synthesis of designs targeted to a non-Xilinx technology when the Built-in Symbols have been used on a block diagram with EDIF set as the default language for the generated code.

2) Active-HDL provides the IEEE library that includes the packages specified by Standard VITAL ASIC Modeling Specification, version 95 (IEEE Std 1076.4-1995) and 2000 (IEEE Std 1076.4-2000). After the installation, the IEEE library containing packages coming from IEEE Std 1076.4-2000 is mapped by default.

To use the IEEE library containing packages coming from IEEE Std 1076.4-1995:

1. Choose the Execute macro option from the Tools menu.

2. In the Execute macro window, go to the $aldec\Vlib\vital95\src directory and point to the remap_ieee.do macro.

3. Click the Open button. As a result of the macro execution, the IEEE library containing packages specified in IEEE Std 1076.4-1995 is mapped. To re-map the library, repeat step #2 selecting the remap_ieee.do macro stored in the $aldec\Vlib\ieee\src directory.

3) For additional information about the remaining packages, i.e. the packages for which the Active-HDL simulation kernel does not provide the built-in acceleration, refer to the Packages of IEEE Library section of the VHDL Support topic (User Guide | Using Active-HDL | Compilation | VHDL Compilation).

NOTE: The pre-compiled vendor libraries delivered with Active-HDL 9.3 require the IEEE library containing packages coming from IEEE Std 1076.4-2000. After the IEEE library is re-mapped, you will need to re-compile the vendor libraries.

Vendor-Specific Libraries

The below tables present vendor-specific libraries (for synthesis and implementation tools) that are supported by the recently released version, update, or service pack of Active-HDL. Please, note that the installation program of an individual service pack does not include library updates. Both the current and previous versions of the vendor libraries can be downloaded from the Aldec Update Center home page or by selecting Download Active-HDL updates from the Help | Aldec on the Web menu.

The following libraries used in post-synthesis simulation tools are supported in the current version of Active-HDL:

Table 4

The following simulation libraries for implementation tools are supported in the current version of Active-HDL:

Table 5

NOTES:
1) The logical_mappings.do macros are delivered for the POLARPRO and POLARPRO_VER libraries. They are stored in the \Vlib\polarpro and \Vlib\polarpro_ver subfolders and allow logical remapping to the QLPRIMS and QLPRIMS_VER libraries, respectively.
2) All the schematic libraries delivered with this version of Active-HDL are compiled with Level 3 (-O3) as the default optimization level.
3) The Vivado libraries are installed but they are not mapped if selected along with the ISE libraries during the installation of Active-HDL (not applicable if the libraries are installed with the use of the stand-alone library installation wizard). In order to use the Vivado libraries, they need to be attached manually. Prior to attaching some Vivado libraries, detaching ISE libraries of the same names (e.g. UNIMACRO, XILINXCORELIB_VER, etc.) may be required.
4) The logical_mappings.do macros are delivered for the AXCELERATOR_GCLR, AXCELERATOR_GPSET, AXCELERATOR_GCLR_VER, and AXCELERATOR_GPSET_VER libraries. They are stored in the \Vlib\axcelerator_gclr, \Vlib\axcelerator_gpset, \Vlib\axcelerator_gclr_ver, and \Vlib\axcelerator_gpset_ver subfolders and allow logical remapping to the AXCELERATOR and AXCELERATOR_VER libraries, respectively.

Updating System Libraries

This section describes a procedure for updating (recompiling) the system libraries. The typical reasons for recompiling a system library are:

• Newer versions of library source files from which a library was created.

• An older version of the compiler used to compile a library. In this case, you must recompile the library to make it usable

To update a library, follow the procedure described below:

1. Start Active-HDL.

2. Choose Open from the File menu. In the Open dialog box, locate the folder where the library you want to update resides (referred to as a library folder). Libraries are stored in the \Vlib subfolder of the Active-HDL installation folder (by default, C:\Aldec\Active-HDL 9.3\Vlib). The library folder should contain an ADF file for a temporary design that includes all source files the library is built from. Select this file, and then click Open to load the design. In addition to the library sources, the design includes a special macro file used to update the library.

3. Choose Add Files to Design from the Design menu. Using the Add Files to Design dialog box, find and select newer versions of source files. Make sure that the Make local copy option is selected. Click the Add button. You will be prompted to confirm overwriting the existing sources. Click Yes.

NOTE: If you only want to recompile the existing sources, skip the above step.

4. Empty the previous contents of the library by typing in the Console window:

clearlibrary

NOTE: You may skip the above step if you use the same version of the compiler with which the library was originally created.

5. To re-compile the library, execute the macro file attached to the temporary design. To do so, right-click the macro file name on the Files tab of the Design Browser, and then choose Execute from the shortcut menu. The library will be updated.

6. If you have added some new source files to the design which were not included in the library, you must compile them manually. To compile a new source file, right-click it (on the Files tab of Design Browser), and then choose Compile from the shortcut menu.

7. Close the design by choosing Close Design from the File menu.

NOTES:
1. Do not recompile libraries that have built-in acceleration.
2. The complete and pre-compiled vendor libraries also can be downloaded from the Aldec web site.
3. Before you start updating libraries, you may need to set them as writable. To do so, choose the library to update and issue the setlibrarymode command or use the Read/Write option from the pop-up menu in the Library Manager window.

Source Files for IEEE Packages

The following IEEE standard packages are shipped in pre-compiled versions without original source files:

• IEEE_BIT_CONTEXT (ieee_std_synthesis_contexts.vhdl, May 29 2009)

• IEEE_STD_CONTEXT (ieee_std_synthesis_contexts.vhdl, May 29 2009)

• FIXED_FLOAT_TYPES (fixed_float_types.vhdl, April 10 2008)

• FIXED_GENERIC_PKG (fixed_generic_pkg.vhdl, April 10 2008)

• FIXED_PKG (fixed_pkg.vhdl, April 10 2008)

• FLOAT_PKG (float_pkg.vhdl, April 10 2008)

• FLOAT_GENERIC_PKG (float_generic_pkg.vhdl, April 10 2008)

• NUMERIC_BIT (numeric_bit.vhdl, April 10 2008)

• NUMERIC_BIT_UNSIGNED (numeric_bit_unsigned.vhdl, April 10 2008)

• NUMERIC_STD (numeric_std.vhdl, April 10 2008)

• NUMERIC_STD_UNSIGNED (numeric_std_unsigned.vhdl, April 10 2008)

• MATH_REAL (math_real.vhdl, April 10 2008)

• MATH_COMPLEX (math_complex.vhdl, April 10 2008)

• WAVES_1164_DECLARATIONS (declarations.vhd, May 1 1997)

• WAVES_1164_FRAMES (frames.vhd, May 1 1997)

• WAVES_1164_UTILITIES (testbench_utilities.vhd, May 1 1997)

• WAVES_INTERFACE (waves_interface.vhd, May 1 1997)

The lack of source files prevents full debugging of models referencing subprograms defined in these packages. To obtain the source files contact:

IEEE Contact Center
Phone: +1 800 678 4333 (USA and Canada) or +1 732 981 0060 (Worldwide)
Fax: +1 732 562 6380
E-mail: contactcenter@ieee.org

Help and Documentation Files

Active-HDL provides the updated help information in the Compiled HTML (*.chm) format. Microsoft Internet Explorer 4.0 or higher is required to view the documentation in this format (it does not have to be set as the default Internet browser on your system). To open the help documentation, choose Product Help from the Help menu. You can also load it by double-clicking the Umbrella.chm file stored in the \Books subfolder. Unless specified otherwise, all documentation files reside in the \Book subfolder of the Active-HDL installation folder.

In addition, Active-HDL provides EVITA, the enhanced VHDL/Verilog tutorial available in the \Evita subfolder, and the history of Release Notes coming from older versions of Active-HDL (\Books\Release_History).

The following documentation help files are shipped with Active-HDL:

• Active-HDL Main Help Page (umbrella.chm)

• Active-HDL User Guide (avhdl.chm)

• Release Notes (relnotes.chm)

• License Information Guide (licensenotes.chm)

• Message Reference Guide (msgref.chm)

• OVA Reference Guide (ovaref.chm)

• PLI Reference Guide (pliref.chm)

• PSL Reference Guide (pslref.chm)

• SystemVerilog Reference Guide (svref.chm)

• Verilog Reference Guide (vlogref.chm)

• VHDL Reference Guide (vhdlref.chm)

• VTL Reference Guide (vtlref.chm)

• HDL Entry and Simulation Tutorial (tutavhdl.chm)

• Mixed Mode Entry and Simulation Tutorial (tutbde.chm)

• State Machine Entry and Debugging Tutorial (tutfsm.chm)

• VHDL Testbench Tutorial (tuttbch.chm)

• VHDL Entry and Simulation Tutorial (tutvhdl.chm)

• Verilog Entry and Simulation Tutorial (tutvlog.chm)

• Mixed VHDL-Verilog Tutorial (tutmixed.chm)

• Code Coverage Tutorial (tutcc.chm)

• VHDL Configuration Tutorial (tutconf.chm)

• Post Simulation Debug Tutorial (tutpsd.chm)

• Tcl/Tk Reference Manual (tcl85.hlp, tk85.hlp)

NOTE: The updated Active-HDL documentation is not limited and provides the help system for all features available in the full version of Active-HDL (Expert Edition (EE)). If you have a limited edition of Active-HDL, you are still able to get the information about all available features. Contact Aldec for more information about license updates and new Active-HDL features.